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low voltage intel ? pentium ? iii processor with 512kb l2 cache datasheet product features the lv intel ? pentium ? iii processor 512k is designed for high-performance computing applications. it is binary compatible with previous intel architecture processors. the processor provides great performance for applications that run on advanced operating systems such as microsoft* windows* nt, microsoft windows 2000, microsoft windows xp and linux. this is achieved by integrating the best attributes of intel processors?the dynamic execution, dual independent bus architecture plus intel ? mmx? technology, and internet streaming simd extensions?to bring a new level of performance to system designs. the lv intel pentium iii processor with 512 kbytes of l2 cache extends the power of the intel pentium iii processor with performance headroom for applied computing and communications applications, and for high density web serving and other front-end operations. systems based on the lv intel pentium iii processor 512k also include the latest features to simplify system management and lower the cost of ownership. available at 800, 933, and 1000 mhz with a 133 mhz system bus frequency at 1.15 v (lv) 512-kbyte advanced transfer cache (on- die, full speed level two (l2) cache with error correcting code (ecc)) dual independent bus (dib) architecture: separate dedicated external system bus and dedicated internal high-speed cache bus internet streaming simd extensions for enhanced video, sound and 3d performance binary compatible with applications running on previous members of the intel microprocessor line dynamic execution micro architecture power management capabilities ? system management mode ? multiple low-power states optimized for 32-bit applications running on advanced 32-bit operating systems micro-fcbga packaging technology ? supports small form factor designs ? exposed die enables more efficient heat dissipation integrated high performance 16 kbyte instruction and 16 kbyte data, nonblocking, level one cache quad quadword wide (256-bit) cache data bus provides extremely high throughput on read/store operations 8-way cache associativity provides improved cache hit rate on reads/store operations error-correcting code for system bus data dual processor capable order number: 273673-005 jan 2003
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the low voltage intel ? pentium ? iii processor 512k may contain design defects or errors known as errata that may cause the product to deviate from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents that have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2003 alertview, i960, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, commerce cart, ct connect, ct media, dialogic, dm3, etherexpress, etox, flashfile, gatherround, i386, i486, icat, icomp, insight960, instantip, intel, intel logo, intel386, i ntel486, intel740, inteldx2, inteldx4, intelsx2, intel chatpad, intel create&share, intel dot.station, intel gigablade, intel inbusiness, intel in side, intel inside logo, intel netburst, intel netstructure, intel play, intel play logo, intel pocket concert, intel singledriver, intel speedstep, intel str ataflash, intel teamstation, intel weboutfitter, intel xeon, intel xscale, itanium, jobanalyst, landesk, lanrover, mcs, mmx, mmx logo, netport, netportexpre ss, optimizer logo, overdrive, paragon, pc dads, pc parents, pentium, pentium ii xeon, pentium iii xeon, performance at your command, proshar e, remoteexpress, screamline, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside, the journey inside, this way in, tokenexpress, trillium, vivonic, and vtune are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others.
datasheet 3 contents contents 1.0 introduction ............................................................................................................................... ..... 7 1.1 overview.................................................................................................................... ........... 7 1.2 terminology ................................................................................................................. ......... 8 1.3 related documents ........................................................................................................... ...9 2.0 processor features .....................................................................................................................10 2.1 512-kbyte on-die integrated l2 cache .............................................................................10 2.2 data prefetch logic ......................................................................................................... ...10 2.3 processor system bus and v ref.............................................................................................................. 10 2.4 differential clocking ....................................................................................................... .....11 2.5 clock control and low power states .................................................................................11 2.5.1 normal state?state 1 ...........................................................................................12 2.5.2 autohalt power down state?state 2 ................................................................12 2.5.3 stop-grant state?state 3 .....................................................................................13 2.5.4 halt/grant snoop state?state 4 ........................................................................13 2.5.5 sleep state?state 5 .............................................................................................13 2.5.6 clock control .........................................................................................................14 2.6 power and ground balls .....................................................................................................1 4 2.7 processor system bus clock and processor clocking ......................................................14 2.8 processor system bus unused balls .................................................................................15 2.9 lv intel pentium iii processor 512k cpuid.......................................................................15 3.0 electrical specifications .............................................................................................................16 3.1 processor system bus signal groups................................................................................16 3.1.1 asynchronous vs. synchronous for system bus signals ......................................17 3.1.2 system bus frequency select signals ..................................................................17 3.2 single-ended clocking bsel[1:0] implementation.............................................................17 3.3 differential host bus clocking routing ...............................................................................18 3.3.1 differential clocking bsel[1:0] implementation ....................................................18 3.4 signal state in low-power states ......................................................................................19 3.4.1 system bus signals ...............................................................................................19 3.4.2 cmos and open-drain signals.............................................................................19 3.4.3 other signals .........................................................................................................19 3.5 test access port (tap) connection ...................................................................................20 3.6 power supply requirements ..............................................................................................20 3.6.1 decoupling guidelines ...........................................................................................20 3.6.2 processor vcc core decoupling ...........................................................................20 3.6.3 voltage planes.......................................................................................................21 3.7 voltage identification ...................................................................................................... ....21 3.8 system bus clock and processor clocking........................................................................24 3.9 maximum ratings ............................................................................................................. ..24 3.10 dc specifications .......................................................................................................... .....25 3.11 ac specifications.......................................................................................................... ......30 3.11.1 system bus, clock, apic, tap, cmos, and open-drain ac specifications........30
contents 4 datasheet 4.0 system signal simulations ......................................................................................................... 40 4.1 system bus clock (bclk) and picclk dc specifications and ac signal quality specifications .......................................................... 40 4.2 agtl ac signal quality specifications .............................................................................. 42 4.3 non-agtl signal quality specifications ............................................................................ 43 4.3.1 pwrgood signal quality specification............................................................... 44 4.3.2 vtt_pwrgd signal quality specification............................................................ 44 5.0 mechanical specifications .......................................................................................................... 46 5.1 surface mount micro-fcbga package .............................................................................. 46 5.2 signal listings............................................................................................................. ........ 50 6.0 thermal specifications and design considerations ................................................................ 57 6.1 thermal specifications ...................................................................................................... .57 6.1.1 thermtrip# requirement .................................................................................. 57 6.1.2 thermal diode ....................................................................................................... 58 7.0 processor interface ..................................................................................................................... 59 7.1 alphabetical signals reference.......................................................................................... 59 7.2 signal summaries............................................................................................................ ... 67 figures 1 agtl bus topology ............................................................................................................. ...... 11 2 stop clock state machine ...................................................................................................... .... 12 3 differential/single-ended clocking example .............................................................................. 15 4 single ended clock bsel circuit (133 mhz) ............................................................................. 18 5 differential clock bsel circuit ............................................................................................... .... 19 6 pll filter .................................................................................................................... ................ 21 7v tt power good and bus select interconnect diagram ............................................................ 23 8 power supply current slew rate (dicc core /dt)......................................................................... 26 9vcc core static and transient tolerance ................................................................................... 27 10 bclk (single ended)/picclk/tck generic clock timing waveform ...................................... 35 11 differential bclk/bclk# waveform (common mode) .............................................................. 35 12 bclk/bclk# waveform (differential mode) .............................................................................. 36 13 valid delay timings .......................................................................................................... .......... 36 14 setup and hold timings ....................................................................................................... ...... 37 15 cold/warm reset and configuration timings ............................................................................ 37 16 power-on sequence and reset timings ................................................................................... 38 17 test timings (boundary scan) ................................................................................................. .. 39 18 test reset timings........................................................................................................... .......... 39 19 bclk (single-ended)/picclk generic clock waveform .......................................................... 41 20 maximum acceptable overshoot/undershoot waveform........................................................... 42 21 noise estimation............................................................................................................. ............ 45 22 micro-fcbga package ? top and bottom isometric views ...................................................... 47 23 micro-fcbga package ? top and side views .......................................................................... 48 24 micro-fcbga package - bottom view....................................................................................... 49 25 ball map - top view .......................................................................................................... ......... 50
datasheet 5 contents tables 1 related documents ............................................................................................................. ......... 9 2 lv/ulv intel? pentium? iii processor 512k cpuid .................................................................15 3 system bus signal groups...................................................................................................... ...16 4 bsel[1:0] encoding............................................................................................................ ........17 5 lv intel pentium iii processor 512k vid values ........................................................................22 6 lv intel pentium iii processor 512k absolute maximum ratings ..............................................24 7 power specifications for lv intel pentium iii processor 512k ...................................................25 8vcc core static and transient tolerance ...................................................................................27 9 agtl signal group levels specifications..................................................................................28 10 processor agtl bus specifications...........................................................................................2 8 11 clkref, apic, tap, cmos, and open-drain signal group dc specifications ......................29 12 system bus clock ac specifications (differential).....................................................................30 13 system bus clock ac specifications (133 mhz, single-ended) ................................................31 14 valid lv intel pentium iii processor 512k frequencies .............................................................32 15 agtl signal groups ac specifications .....................................................................................32 16 cmos and open-drain signal groups ac specifications .........................................................32 17 reset configuration ac specifications and power on timings .................................................33 18 apic bus signal ac specifications ............................................................................................ 33 19 tap signal ac specifications................................................................................................. ....34 20 bclk (differential) dc specifications and ac signal quality specifications .............................40 21 bclk (single-ended) dc specifications and ac signal quality specifications.........................40 22 picclk dc specifications and ac signal quality specifications ..............................................41 23 133 mhz agtl signal group overshoot/undershoot tolerance at the processor core.......................................................................................................... .......43 24 non-agtl signal group overshoot/undershoot tolerance at the processor core ..................43 25 micro-fcbga package mechanical specifications ....................................................................46 26 signal list by ball number................................................................................................... .......51 27 signal listing by signal name ................................................................................................ ....54 28 voltage and no-connect ball locations .....................................................................................56 29 lv intel pentium iii processor 512k thermal design power .....................................................57 30 thermtrip# time requirement ..............................................................................................57 31 thermal diode interface ...................................................................................................... .......58 32 thermal diode parameters..................................................................................................... ....58 33 signal description........................................................................................................... ............59 34 input signals ................................................................................................................ ...............67 35 output signals ............................................................................................................... .............68 36 input/output signals (single driver) ......................................................................................... ..68 37 input/output signals (multiple driver)....................................................................................... ..68
contents 6 datasheet revision history date revision description march 2002 -001 first release of this document. september 2002 -002 added 933mhz data and 06b4 stepping september 2002 -003 added chapter 6 and 7 january 2003 -004 added 1000mhz data january 2003 -005 updated table 14, power on configuration bits
lv intel ? pentium ? iii processor 512k datasheet 7 1.0 introduction using intel?s advanced 0.13-micron process technology with copper interconnect, the low voltage (lv) intel ? pentium ? iii processor 512k offers high-performance and low-power consumption. key performance features include internet streaming simd instructions, an advanced transfer cache architecture, and a processor system bus speed of up to 133 mhz. these features are offered in a micro-fcbga package for surface mount boards. all of these technologies make outstanding performance possible for applied computing applications. the 512 kbyte integrated (on-die) level 2 (l2) cache, which is based on the advanced transfer cache architecture, runs at the processor core speed and is designed to help improve performance. it complements the system bus by providing critical data faster and reducing total system power consumption. the processor?s 64-bit wide assisted gunning transceiver logic (agtl) system bus provides a glue-less interface for a memory controller hub. this document provides the electrical, mechanical, and thermal specifications for the lv intel pentium iii processor 512k in the micro-fcbga package at 800, 933, and 1000 mhz (1.15 v, lv). with a 133 mhz system bus. for information not provided in this document, refer to the documents listed in table 1 . 1.1 overview ? performance features ? supports the intel architecture with dynamic execution ? supports the intel architecture mmx? technology ? supports streaming simd extensions for enhanced video, sound, and 3d performance ? integrated intel floating point unit compatible with the ieee 754 standard ? data prefetch logic ? on-die primary (l1) instruction and data caches ? 4-way set associative, 32-byte line size, 1 line per sector ? 16-kbyte instruction cache and 16-kbyte write-back data cache ? cacheable range controlled by processor programmable registers ? on-die second level (l2) cache ? 8-way set associative, 32-byte line size, 1 line per sector ? operates at full core speed ? 512-kbyte ecc protected cache data array ? agtl system bus interface ? 64-bit data bus, 133-mhz operation ? dual processor support ? integrated termination ? thermal diode for measuring processor temperature
lv intel ? pentium ? iii processor 512k 8 datasheet 1.2 terminology term definition # a ?#? symbol following a signal name indicates that the signal is active low. this means that when the signal is asserted (based on the name of the signal) it is in an electrical low state. otherwise, signals are driven in an electrical high state when they are asserted. in state machine diagrams, a signal name in a condition indicates the condition of that signal being asserted ! indicates the condition of that signal not being asserted. for example, the condition ?!stpclk# and hs? is equivalent to ?the active low signal stpclk# is unasserted (i.e., it is at 1.5 v) and the hs condition is true.? l electrical low signal levels h electrical high signal levels 0 logical low. for example, bd[3:0] = ?1010? = ?hlhl? refers to a hexadecimal ?a,? and d[3:0]# = ?1010? = ?lhlh? also refers to a hexadecimal ?a.? 1 logical high. for example, bd[3:0] = ?1010? = ?hlhl? refers to a hexadecimal ?a,? and d[3:0]# = ?1010? = ?lhlh? also refers to a hexadecimal ?a.? tbd specifications that are yet to be determined and will be updated in future revisions of the document. x don?t care condition lv dp pentium iii processor 512k at a core voltage of 1.15 v. dp dual processor up single processor (uniprocessor)
lv intel ? pentium ? iii processor 512k datasheet 9 1.3 related documents table 1. related documents document order number p6 family of processors hardware developer?s manual 244001 ia-32 intel ? architecture software developer?s manual ? volume i: basic architecture ? volume ii: instruction set reference ? volume iii: system programming guide 245470 245471 245472 vrm 8.5 dc-dc converter design guidelines 249659 low voltage intel ? pentium ? iii processor 512k dual processor platform design guide 273674 low voltage intel ? pentium ? iii processor 512k (dp) thermal design guide 273675 low voltage intel ? pentium ? iii processor 512k/815e chipset platform design guide 273676 intel ? pentium ? iii processor specification update 244453 intel processor identification and the cpuid instruction 241618
lv intel ? pentium ? iii processor 512k 10 datasheet 2.0 processor features 2.1 512-kbyte on-die integrated l2 cache the lv intel pentium iii processor 512k has a 512-kbyte on-die integrated level 2 (l2) cache. the l2 cache runs at the processor core speed and the increased cache size provides superior processing power. 2.2 data prefetch logic the lv intel pentium iii processor 512k features data prefetch logic that speculatively fetches data to the l2 cache before an l1 cache request occurs. this reduces transactions between the cache and system memory, and reduces or eliminates bus cycle penalties, which improves performance. the processor also includes extensions to memory order and reorder buffers that boost performance. 2.3 processor system bus and v ref the lv intel pentium iii processor 512k uses the original low voltage signaling of the gunning transceiver logic (gtl) technology for the system bus. the gtl system bus operates at 1.25 v signal levels while gtl+ operates at 1.5 v signal levels. the gtl+ signal technology is used by the intel ? pentium ? pro, intel pentium ii and intel pentium iii processors. current p6 family processors differ from the intel pentium pro processor in their output buffer implementation. the buffers that drive the system bus signals on the lv intel pentium iii processor 512k are actively driven to v tt for one clock cycle after the low to high transition to improve rise times. these signals are open-drain and require termination to a supply. because this specification is different from the standard gtl specification, it is referred to as agtl, or assisted gtl in this and other documentation related to the lv intel pentium iii processor 512k. agtl logic and agtl+ logic are not compatible with each other due to differences with the signal switching levels. the lv intel pentium iii processor 512k cannot be installed into platforms where the chipset only supports the agtl+ signal levels. for more information on agtl or agtl+ routing, please refer to the appropriate platform design guide. agtl inputs use differential receivers that require a reference voltage (v ref ). v ref is used by the differential receivers to determine if the input signal is a logical 0 or a logical 1. the v ref signal is typically implemented as a voltage divider on the platform. noise decoupling is critical for the v ref signal. refer to the platform design guide for the recommended decoupling requirements. another important issue for the agtl system bus is termination. system bus termination is used to pull each signal to a high voltage level and to control reflections on the transmission line. the processor contains on-die termination resistors that provide termination for one end of the system bus. the other end of the system bus should also be terminated by resistors placed on the platform or on-die termination within the agent. it is recommended that the system bus is implemented using dual-end termination (det) to meet the timings and signal integrity specified by the lv intel pentium iii processor 512k. figure 1 is a schematic representation of the agtl bus topology for the lv intel pentium iii processor 512k; in this figure the chipset does not have on-die termination.
lv intel ? pentium ? iii processor 512k datasheet 11 note: the reset# signal requires a discrete external termination resistor on the system board. the agtl bus depends on incident wave switching. therefore, timing calculations for agtl signals are based on flight time as opposed to capacitive deratings. analog signal simulations of the system bus, including trace lengths, are highly recommended, especially when the recommended layout guidelines are not followed. note: r3 and r4 determine the nominal values of r1 and r2, respectively. please refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for further dual processor system bus layout and topology information. 2.4 differential clocking the lv intel pentium iii processor 512k supports differential clocking. differential clocking requires the use of two complementary clocks: bclk and bclk#. benefits of differential clocking include easier scaling to lower voltages, reduced emi, and less jitter. the lv intel pentium iii processor 512k also supports single-ended clocking. note: all references to bclk in this document also apply to bclk#. 2.5 clock control and low power states the processor allows the use of autohalt, stop-grant, and sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 2 for a visual representation of the processor low power states. figure 1. agtl bus topology chipset cpu0 cpu1 l0 l1 l2 rttctrl v tt r1 r2 v tt r3 rttctrl r4
lv intel ? pentium ? iii processor 512k 12 datasheet for the processor to fully realize the low current consumption of the stop-grant and sleep states, a model specific register (msr) bit must be set. for the msr at 02ah (hex), bit 26 must be set to a ?1? (this is the power on default setting) for the processor to stop all internal clocks during these modes. for more information, see the intel architecture software developer?s manual, volume 3: system programming guide . 2.5.1 normal state?state 1 this is the normal operating state for the processor. 2.5.2 autohalt power down state?state 2 autohalt is a low power state that is entered when the processor executes the halt instruction. the processor transitions to the normal state upon the occurrence of smi#, init#, or lint[1:0] (nmi, intr). reset# causes the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the autohalt power down state. see the intel architecture software developer's manual, volume iii: system programmer's guide for more information. figure 2. stop clock state machine 2. auto halt power down state bclk running snoops and interrupts allowed 1. normal state normal execution 4. halt/grant snoop state bclk running service snoops to caches 3. stop grant state bclk running snoops and interrupts allowed 5. sleep state bclk runing no snoops or interrupts allowed halt instruction and halt bus cycle generated snoop event occurs snoop event serviced init#, binit#, intr, nmi, smi#, reset# stpclk# asserted stpclk# de-asserted s t p c l k # a s s e r t e d s t p c l k # d e - a s s e r t e d slp# asserted slp# de-asserted snoop event occurs snoop event serviced
lv intel ? pentium ? iii processor 512k datasheet 13 flush# is serviced during the autohalt state. once the flush# is complete the processor returns to the autohalt state. the system can generate a stpclk# while the processor is in the autohalt power down state. when the system deasserts the stpclk# interrupt, the processor returns execution to the halt state. 2.5.3 stop-grant state?state 3 the stop-grant state on the processor is entered when the stpclk# signal is asserted. since the agtl signal balls receive power from the system bus, these balls should not be driven. (allowing the level to return to v tt ) to minimize the power drawn by the termination resistors in this state. in addition, all other input balls on the system bus should be driven to the inactive state. binit# and flush# are not serviced during the stop-grant state. reset# causes the processor to immediately initialize itself, but the processor stays in stop-grant state. a transition back to the normal state occurs with the deassertion of the stpclk# signal. a transition to the halt/grant snoop state occurs when the processor detects a snoop on the system bus (see section 2.5.4 ). a transition to the sleep state (see section 2.5.5 ) occurs with the assertion of the slp# signal. while in stop-grant state, smi#, init#, and lint[1:0] are latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event is recognized and serviced upon return to the normal state. 2.5.4 halt/grant snoop state?state 4 the processor responds to snoop transactions on the system bus while in stop-grant state or in autohalt power down state. during a snoop transaction, the processor enters the halt/grant snoop state. the processor stays in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). after the snoop is serviced, the processor returns to the stop-grant state or autohalt power down state, as appropriate. 2.5.5 sleep state?state 5 the sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sleep state can only be entered from the stop-grant state. once in the stop-grant state, the slp# ball can be asserted, causing the processor to enter the sleep state. the slp# ball is not recognized in the normal or autohalt states. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp# or reset#) are allowed on the system bus while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior.
lv intel ? pentium ? iii processor 512k 14 datasheet if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# ball specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. 2.5.6 clock control bclk provides the clock signal for the processor and on-die l2 cache. during autohalt power down and stop-grant states, the processor processes a system bus snoop. the processor does not stop the clock to the l2 cache during autohalt power down or stop-grant states. entrance into the halt/grant snoop state allows the l2 cache to be snooped, similar to the normal state. when the processor is in sleep state, it does not respond to interrupts or snoop transactions. during the sleep state, the internal clock to the l2 cache is not stopped. picclk should not be removed during the autohalt power down or stop-grant states. picclk can be removed during the sleep state. 2.6 power and ground balls the operating voltage for the lv intel pentium iii processor 512k is the same for the core and the l2 cache. v cc core is defined as the power balls that supply voltage to the processor?s core and cache. the voltage regulator module (vrm) and the voltage regulator are controlled by the five voltage identification (vid) signals driven by the processor. the vid signals specify the voltage required by the processor core. refer to section 3.7 for further details on the vid voltage settings. the lv intel pentium iii processor 512k has 81 v cc core , 8 v ref , 38 v tt , and 146 v ss inputs. the v ref inputs are used as the agtl reference voltage for the processor. the v tt inputs (1.25 v) are used to provide an agtl termination voltage to the processor. v cc cmos1.5 and v cc cmos1.8 and v cc cmos2.0 are not voltage input balls to the processor. they are voltage sources for the pullup resistors that are connected to cmos (non-agtl) input/output signals that are driven to/from the processor. the v ss inputs are ground balls for the processor core and l2 cache. on the platform, all v cc core balls must be connected to a voltage island (an island is a portion of a power plane that has been divided, or it is an entire voltage plane) to minimize any voltage drop that may occur due to trace impedance. it is also highly recommended that the platform provide either a voltage island or a wide trace for the v tt balls. similarly, all v ss balls must be connected to a system ground plane. refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for more information. 2.7 processor system bus clock and processor clocking the lv intel pentium iii processor 512k has an auto-detect mechanism that allows the processor to use either single-ended or differential signaling for the system bus and processor clocking. the processor checks to see if the signal on ball ad1 is toggling. if this signal is toggling then the processor operates in differential mode. refer to figure 3 for an example on differential clocking. resistor values and clock topology are listed in the appropriate platform design guide for a differential implementation. note: in this document, references to bclk also apply to its complement signal (bclk#) in differential implementations and when noted otherwise.
lv intel ? pentium ? iii processor 512k datasheet 15 2.8 processor system bus unused balls all reserved balls must remain unconnected unless specifically noted. connection of these balls to v cc core , v ref , v ss , v tt or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. see section 5.2 for a ball listing of the processor and the location of each ball that should be left unconnected (nc). for reliable operation, always connect unused inputs or bidirectional signals to their deasserted signal level. the pull-up or pull-down resistor values are system dependent and should be chosen so that the logic high (v ih ) and logic low (v il ) requirements are met. see table 11 for level specifications of non-agtl signals. for unused agtl inputs, the on-die termination will be sufficient. no external r tt is necessary on the motherboard. for unused cmos inputs, active low signals should be connected to v cc cmos1.5 through a pull-up resistor and should meet v ih requirements. unused active high cmos inputs should be connected to ground (v ss ) through a pull-down resistor and should meet v il requirements. unused cmos outputs can be left unconnected. a resistor must be used when tying bidirectional signals to power or ground. when tying a signal to power or ground, a resistor will also allow for system testability. 2.9 lv intel pentium iii processor 512k cpuid after a power-on reset or when the cpuid version information is loaded, the eax and ebx registers contain the values shown in table 2. table 2. lv/ulv intel? pentium? iii processor 512k cpuid figure 3. differential/single-ended clocking example bclk bclk# clock driver processor or chipset clock driver bclk processor or chipset eax[31:0] ebx[7:0] reserved [31:14] type [13:12] family [11:8] model [7:4] stepping [3:0] brand id x06bx2 x06bx4
lv intel ? pentium ? iii processor 512k 16 datasheet 3.0 electrical specifications 3.1 processor system bus signal groups to simplify the following discussion, the processor system bus signals have been combined into groups by buffer type. all p6 family processor system bus outputs are open drain and require termination resistors. however, the lv intel pentium iii processor 512k includes on-die termination for agtl signals. this makes it unnecessary to place termination resistors on the platform, except in the case of the reset# signal, which still requires external termination. agtl input signals have differential input buffers that use v ref as a reference signal. agtl output signals require termination to 1.25 v. in this document, the term ?agtl input? refers to the agtl input group and to the agtl i/o group when this group is receiving signals. similarly, ?agtl output? refers to the agtl output group and to the agtl i/o group when this group is driving signals. the pwrgood signal input is a 1.8 v signal level and must be pulled up to v cc cmos1.8 . the vtt_pwrgd is not 1.8 v tolerant and must be connected to v tt ( 1.25 v). other cmos inputs (a20m#, ignne#, init#, lint0/intr, lint1/nmi, preq#, smi#, slp#, and stpclk#) are only 1.5 v tolerant and must be pulled up to v cc cmos1.5 . the cmos, apic, and tap outputs are open drain and must be pulled to the appropriate level to meet the input specifications of the interfacing device. the groups and the signals contained within each group are shown in table 3 . refer to ?processor interface? on page 59 for a description of these signals. table 3. system bus signal groups (sheet 1 of 2) group name signals agtl input bpri#, defer#, reset#, rsp#, br1# agtl output prdy# agtl i/o a[35:3]#, ads#, aerr#, ap[1:0]#, berr#, binit#, bnr#, bp[3:2]#, bpm[1:0]#, br0#, d[63:0]#, dbsy#, dep[7:0]#, drdy#, hit#, hitm#, lock#, req[4:0]#, rp#, rs[2:0]#, trdy# 1.5 v cmos input a20m#, flush#, ignne#, init#, lint0/intr, lint1/nmi, preq#, slp#, smi#, stpclk# 1.8 v cmos input pwrgood 1.5 v open drain output ferr#, ierr#, thermtrip# 3.3 v open drain output bsel[1:0], vid[3:0, 25mv] 1.25 v input vtt_pwrgd clock bclk, bclk# (differential mode) 2.5 v clock input bclk (single ended mode) notes: 1. v cccore is the power supply for the core logic. 2. pll1 and pll2 are power/ground for the pll analog section. see ?voltage planes? on page 21 for details. 3. v tt is the power supply for the system bus buffers. 4. v ref is the voltage reference for the agtl input buffers. 5. v ss is system ground.
lv intel ? pentium ? iii processor 512k datasheet 17 3.1.1 asynchronous vs. synchronous for system bus signals all agtl signals are synchronous to bclk (bclk/bclk#). all of the cmos, clock, apic, and tap signals can be applied asynchronously to bclk (bclk/bclk#). all apic signals are synchronous to picclk. all tap signals are synchronous to tck. 3.1.2 system bus frequency select signals the bsel[1:0] (select processor system bus speed) signals are used to configure the processor for the system bus frequency. the vtt_pwrgd signal informs the processor to output the bsel signals. during power up the bsel signals are indeterminate for a small period of time. if the clock generator supports this dynamic bsel selection, it should not sample the bsel signals until the vtt_pwrgd signal is asserted. the assertion of the vtt_pwrgd signal indicates that the bsel signals are stable and driven to a final state by the processor. table 4 shows the encoding scheme for bsel[1:0]. the only supported system bus frequency for the lv pentium iii processor 512k is 133 mhz. if another frequency is used, the processor is not guaranteed to function properly. 3.2 single-ended clocking bsel[1:0] implementation in an lv intel pentium iii processor 512k platform that is using single-ended clocking or a clock source that does not support the vtt_pwrgd protocol, the normal bsel frequency selection process will not work. since the clock generator is not compatible with dynamic bsel assertions, all bsel[1:0] signals should not be connected together. instead, the bsel pins on the clock generator should be pulled-up to 3.3 v through a 1 k ? , 5% resistor. this strapping forces the clock generator into 133 mhz clocking mode. it only supports 133 mhz capable processors. apic clock picclk apic i/o picd[1:0] thermal diode thermdn, thermdp tap input tck, tdi, tms, trst# tap output tdo power/other clkref, vcmos_ref, slewctrl, nchctrl, pll1, pll2, rttctrl, vcc core , v tt , v ref , v ss table 3. system bus signal groups (sheet 2 of 2) notes: 1. v cccore is the power supply for the core logic. 2. pll1 and pll2 are power/ground for the pll analog section. see ?voltage planes? on page 21 for details. 3. v tt is the power supply for the system bus buffers. 4. v ref is the voltage reference for the agtl input buffers. 5. v ss is system ground. table 4. bsel[1:0] encoding bsel[1:0] system bus frequency 11 133 mhz
lv intel ? pentium ? iii processor 512k 18 datasheet 3.3 differential host bus clocking routing lv intel pentium iii processor 512k dual-processor platforms support differential host bus clock drivers. when operating in differential clocking mode, the bclk and bclk#/clkref form a differential pair of clock inputs. the differential pair of traces should be routed with special care and using standard differential signaling techniques. refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for more information. the following sections contain the recommended topology and routing for differential clocking in the lv intel pentium iii processor 512k dual-processor platforms. 3.3.1 differential clocking bsel[1:0] implementation the system bus frequency select signals (bsel[1:0]) are used to select the system bus frequency for the host bus agents. frequency selection is determined by the processor(s) and driven out to the host bus clock generator. all system bus agents must operate at the same 133 mhz frequency. the bsel balls for the processor are open drain signals and rely on a 3.3 v pull-up resistor to set the signal to a logic high level. figure 5 shows the recommended implementation for a differentially clocked system. figure 4. single ended clock bsel circuit (133 mhz) nc nc nc nc processor 1 processor 0 clock driver bsel0 bsel1 bsel0 bsel1 bsel0 bsel1 3.3v 3.3v 1 k ? 5% 1 k ? 5%
lv intel ? pentium ? iii processor 512k datasheet 19 3.4 signal state in low-power states 3.4.1 system bus signals all of the system bus signals have agtl input, output, or input/output drivers. the system bus signals are tri-stated and pulled up by the termination resistors unless they are servicing snoops. 3.4.2 cmos and open-drain signals the cmos input signals are allowed to be in either the logic high or low state when the processor is in a low-power state. in the auto halt state these signals are allowed to toggle. these input buffers have no internal pull-up or pull-down resistors and system logic can use cmos or open- drain drivers to drive them. the open-drain output signals have open drain drivers that require external pull-up resistors. one of the two output signals (ierr#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the processor is functioning normally. the ferr# output can be either tri-stated or driven to v ss when the processor is in a low-power state, depending on the condition of the floating-point unit. 3.4.3 other signals the system bus clocks (bclk, bclk#) must be driven in all of the low-power states. the apic clock (picclk) must be driven whenever bclk and bclk# are driven. otherwise, it is permitted to turn off picclk by holding it at v ss . bclk and bclk# must remain within the dc specifications in table 20 (for differential clocking) and table 21 (for single-ended clocking). in the auto halt state, the apic bus data signals (picd[1:0]) may toggle due to apic bus messages. figure 5. differential clock bsel circuit processor 0 bsel0 bsel1 clock driver 1k ohm 5% 1k ohm 5% 3.3v 3.3v processor 1 bsel0 bsel1
lv intel ? pentium ? iii processor 512k 20 datasheet 3.5 test access port (tap) connection the tap interface is an implementation of the ieee 1149.1 (?jtag?) standard. due to the voltage levels supported by the tap interface, intel recommends that the lv intel pentium iii processor 512k and the other 1.5 v jtag specification compliant devices be placed last in the jtag chain, behind any system devices with 3.3 v or 5.0 v jtag interfaces. a translation buffer should be used to reduce the tdo output voltage of the last 3.3/5.0 v device down to the 1.5 v range that the processor can tolerate. multiple copies of tms and trst# must be provided, one for each voltage level. a debug port and connector may be placed at the start and at the end of the jtag chain that contains the processor, with tdi to the first component coming from the debug port, and tdo from the last component going to the debug port. there are no requirements for placing the processor in the jtag chain, except for those that are dictated by the voltage requirements of the tap signals. 3.6 power supply requirements 3.6.1 decoupling guidelines due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. these fluctuations can cause voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in table 7 . failure to do so can result in timing violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a voltage overshoot). 3.6.2 processor v cc core decoupling the regulator for the v cc core input must be capable of delivering the di cc core /dt (defined in table 7 ) while maintaining the required tolerances (defined in table 9 ). failure to meet these specifications can result in timing violations (during v cc core sag) or a reduced lifetime of the component (during v cc core overshoot). the processor requires both high frequency and bulk decoupling on the system motherboard for proper agtl bus operation. the minimum recommendation for the processor decoupling requirement is listed below. the lv intel pentium iii processor 512k has eight 0.68-f surface mount decoupling capacitors. six 0.68- f capacitors are on v cc core and two 0.68-f capacitors are on v tt . in addition to the package capacitors, sufficient board level capacitors are also necessary for power supply decoupling. these guidelines are as follows: ? high and mid frequency v cc core decoupling ? place twenty-four 0.22-f 0603 capacitors directly under the package on the solder side of the motherboard, using at least two vias per capacitor node. ten 10-f x7r 6.3 v 1206-size ceramic capacitors should be placed around the package periphery near the balls. trace lengths to the vias should be designed to minimize inductance. avoid bending traces to minimize esl. ? high and mid frequency v tt decoupling ? place ten 1-f x7r 0603 ceramic capacitors close to the package. via and trace guidelines are the same as above.
lv intel ? pentium ? iii processor 512k datasheet 21 for additional decoupling requirements, please refer to the appropriate platform design guide for recommended capacitor component value/quantity and placement. 3.6.3 voltage planes all v cc core and v ss balls must be connected to the appropriate voltage plane. all v tt and v ref balls must be connected to the appropriate traces on the system electronics. in addition to the main v cc core , v tt , and v ss power supply signals, pll1 and pll2 provide analog decoupling to the pll section. pll1 and pll2 should be connected according to figure 6 . do not connect pll2 directly to v ss . 3.7 voltage identification there are five voltage identification (vid) balls on the lv intel pentium iii processor 512k. these balls can be used to support automatic selection of v cc core voltages. the vid balls for the lv intel pentium iii processor 512k are open drain signals versus opens or shorts. refer to table 11 for level specifications for the vid signals. these pull-up resistors may be either external logic on the motherboard or internal to the voltage regulator. the vid signals rely on a 3.3 v pull-up resistor to set the signal to a logic high level. the vid balls are needed to fully support voltage specification variations on current and future processors. the voltage selection range for the processor is defined in table 5 . the vid25mv signal is a new signal that allows the voltage regulator or voltage regulator module (vrm) to output voltage levels in 25 mv increments. the voltage regulator or vrm must supply the voltage that is requested or disable itself. in addition to the new signal vid25mv, the lv intel pentium iii processor 512k has a second new signal labeled vtt_pwrgd. the vtt_pwrgd signal informs the platform that the vid and bsel signals are stable and should be sampled. during power-up, the vid signals will be in an indeterminate state for a small period of time. the voltage regulator or the vrm should not latch the vid signals until the vtt_pwrgd signal is asserted by the vrm and is sampled active. the assertion of the vtt_pwrgd signal indicates that the vid signals are stable and are driven to the final state by the processor. refer to figure 16 for power-up timing sequence for the vtt_pwrgd and the vid signals. figure 6. pll filter pll1 pll2 v cct v0027-01 l1 c1 r1 v tt
lv intel ? pentium ? iii processor 512k 22 datasheet table 5. lv intel pentium iii processor 512k vid values vid25mv vid3 vid2 vid1 vid0 v cc core 00100 1.05 10100 1.075 00011 1.10 10011 1.125 00010 1.15 10010 1.175 00001 1.20 10001 1.225 00000 1.25 10000 1.275 01111 1.30 11111 1.325 01110 1.35 11110 1.375 01101 1.40 11101 1.425 01100 1.45 11100 1.475 01011 1.50 11011 1.525 01010 1.55 11010 1.575 01001 1.60 11001 1.625 01000 1.65 11000 1.675 00111 1.70 10111 1.725 00110 1.75 10110 1.775 00101 1.80 10101 1.825 notes: 1. 0 = processor ball connected to v ss and 1 = open on processor; may be pulled up to ttl v ih (3.3v max) on baseboard.
lv intel ? pentium ? iii processor 512k datasheet 23 the vid balls should be pulled up to a 3.3-v level. this may be accomplished with pull-ups internal to the voltage regulator, which ensures valid vid pull-up voltage during power-up and power-down sequences. when external resistors are used for the vid[3:0, 25mv] signal, the power source must be guaranteed to be stable whenever the supply to the voltage regulator is stable. this will prevent the possibility of the processor supply going above the specified v cc core in the event of a failure in the supply for the vid lines. in the case of a dc-to-dc converter, this can be accomplished by using the input voltage to the converter for the vid line pull-ups. a resistor equal to 1 k ? may be used to connect the vid signals to the voltage regulator input. important: intel requires that designs utilize vrm 8.5 and not imvp-ii specifications to meet the lv intel pentium iii processor 512k requirements. to re-emphasize, vrm 8.5 introduces two new signals [vid25mv and vtt_pwrgd] that are used by the lv intel pentium iii processor 512k and platform. failing to connect these two new balls as documented in the design guidelines (provided in the lv intel ? pentium ? iii processor 512k dual processor platform design guide) will prevent the lv intel pentium iii processor 512k from operating at the specified voltage levels and core frequency. figure 7 provides a high-level interconnection schematic. please refer to the vrm 8.5 dc-dc converter design guideline and the appropriate platform design guidelines for further detailed information on the voltage identification and bus select implementation. refer to figure 16 for vid power-up sequence and timing requirements. note: please refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for vtt_pwrgd implementation for an lv intel pentium iii processor 512k platform. separate vrm 8.5 voltage regulators and processor core voltage planes are required for each processor in a dual-processor system. figure 7. v tt power good and bus select interconnect diagram vrm 8.5 voltage regulator processor clock driver vtt vtt_pwrgd (output) vtt_pwrgd (input) vtt r vtt vid[3:0,25mv] vcc_core vcc_core bsel [1:0]
lv intel ? pentium ? iii processor 512k 24 datasheet 3.8 system bus clock and processor clocking the bclk and bclk# clock inputs directly control the operating speed of the system bus interface. all system bus timing parameters are specified with respect to the crossing point of the rising edge of the bclk input and the falling edge of the bclk# input. the lv intel pentium iii processor 512k core frequency is a multiple of the bclk frequency. the processor core frequency is configured during manufacturing. the configured bus ratio is visible to software in the power-on configuration register. multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of signals within the system. clock multiplication within the processor is provided by the internal phase lock loop (pll), which requires constant frequency bclk, bclk# inputs. during reset, the pll requires some amount of time to acquire the phase of bclk and bclk#. this time is called the pll lock latency, which is specified in table 17 on page 33 ; see the ac timing parameter for t18. 3.9 maximum ratings table 6 contains the lv intel pentium iii processor 512k stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating conditions are provided in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. table 6. lv intel pentium iii processor 512k absolute maximum ratings symbol parameter min max unit notes t storage storage temperature ?40 85 c 1 v cc core (abs) supply voltage with respect to v ss ?0.5 1.75 v v tt system bus buffer voltage with respect to v ss ?0.3 1.75 v v in agtl system bus buffer dc input voltage with respect to v ss ?0.3 1.75 v 2 , 3 v in125 1.25 v buffer dc input voltage with respect to v ss ?0.3 1.75 v 4 v in15 1.5 v buffer dc input voltage with respect to v ss ?0.3 2.0 v 5 v in18 1.8 v buffer dc input voltage with respect to v ss ?0.3 2.0 v 6 v in20 2.0 v buffer dc input voltage with respect to v ss ?0.3 2.4 v 7 v in25 2.5 v buffer dc input voltage with respect to v ss ?0.3 3.3 v 8 v invid vid ball dc input voltage with respect to v ss ?3.465 v 9 i vid vid current -0.3 3.6 ma 9 notes: 1. the shipping container is only rated for 65 c. 2. parameter applies to the agtl signal groups only. compliance with both v in agtl specifications is required. 3. the voltage on the agtl signals must never be below ?0.3 or above 1.75 v with respect to ground. 4. parameter applies to clkref, testhi, vtt_pwrgd signals. 5. parameter applies to cmos, open-drain, apic, testlo and tap bus signal groups only. 6. parameter applies to pwrgood signal. 7. parameter applies to picclk signal. 8. parameter applies to bclk signal in single-ended clocking mode. 9. parameter applies to each vid ball individually.
lv intel ? pentium ? iii processor 512k datasheet 25 3.10 dc specifications tables 7 through 11 list the dc specifications for the lv intel pentium iii processor 512k. specifications are valid only while meeting specifications for the junction temperature, clock frequency, and input voltages. the junction temperature range for all dc specifications is 0 c to 100 c. care should be taken to read all notes associated with each parameter. the v cc core tolerances for the lv intel pentium iii processor 512k are not specified as a percentage of nominal. the tolerances are instead specified in the form of load lines for the static and transient cases in table 9 . an illustration of the load lines is shown in figure 9 . table 7. power specifications for lv intel pentium iii processor 512k symbol parameter frequency (mhz) processor signature min typ max unit tolerance v cc core transient v cc core for core logic 1.15 v v cc core,dc static v cc core for core logic 1.15 v v cc cmos1.5 1.5 v cmos voltage 1.5 v 10% v cc cmos1.8 1.8 v cmos voltage 1.8 v 10% v cc cmos3.3 3.3 v cmos voltage 3.3 v 10% v tt v cc for system bus buffers, transient tolerance 1.13 1.25 1.36 v 9% v tt,dc v cc for system bus buffers, static tolerance 1.21 1.25 1.28 v 3% icc core current for v cc core at core frequency 1000 933 800 06b2 06b4 10.94 10.5 9.57 a i tt current for v tt 2.3 a i cc cmos1.5 i cc for v cc cmos1.5 250 ma i cc cmos1.8 i cc for v cc cmos1.8 1ma i cc cmos3.3 i cc for v cc cmos3.3 35 ma icc core,sg processor stop grant current 1.15 v 4.68 a i lvid vid leakage current 0.5 ma
lv intel ? pentium ? iii processor 512k 26 datasheet figure 8. power supply current slew rate (di cc core /dt) slew rate ? 26a load step slew rate (26a) ? icc @ socket 0 5 10 15 20 25 30 0123456 icc @ socket (a) pwl slew rate data time (us) icc @ socket (a) 0.1 26.23 0.15 23.18 0.5 20.03 1 21.10 1.5 21.88 2 22.29 2.5 22.30 3 22.07 3.5 21.78 4 21.58 4.5 21.51 time (s)
lv intel ? pentium ? iii processor 512k datasheet 27 note: the vr must meet the specifications defined in table 8 for every load and load change condition corresponding to the following equations: ? static minimum regulation requirements: vid set point - 25 mv - (4 m ? x icccore) ? static maximum regulation requirements: vid set point + 25 mv - (4 m ? x icccore) ? transient minimum regulation requirements: vid set point - 45 mv - (4 m ? x icccore) ? transient maximum regulation requirements: vid set point + 45 mv - (4 m ? x icccore) table 8. v cc core static and transient tolerance i cc (a) v cc core (v) static min static max trans min trans max 0.0 -25 25 -45 45 1.0 -29 21 -49 41 2.0 -33 17 -53 37 3.0 -37 13 -57 33 4.0 -41 9 -61 29 5.0 -45 5 -65 25 6.0 -49 1 -69 21 7.0 -53 -3 -73 17 8.0 -57 -7 -77 13 9.0 -61 -11 -81 9 10.0 -65 -15 -85 5 11.0 -69 -19 -89 1 12.0 -73 -23 -93 -3 13.0 -77 -27 -97 -7 14.0 -81 -31 -101 -11 15.0 -85 -35 -105 -15 figure 9. v cc core static and transient tolerance -120 -100 -80 -60 -40 -20 0 20 40 60 0. 0 2 .0 4 .0 6.0 8. 0 10 . 0 1 2. 0 14.0 icc (a) vcc droop from vid (mv) static min static max trans min trans max
lv intel ? pentium ? iii processor 512k 28 datasheet table 9. agtl signal group levels specifications symbol parameter min max unit notes v il input low voltage v ref - 0.200 v v ih input high voltage v ref + 0.200 v 1, 2 ron buffer on resistance 16.67 ? 4 i l leakage current for inputs, outputs, and i/o 100 a 3 notes: 1. all inputs, outputs, and i/o balls must comply with the signal quality specifications in section 4.0 . 2. minimum and maximum v tt are given in table 10 . 3. (0 v in 1.25 v +3%) and (0 v out 1.25 v+3%). 4. refer to the processor i/o buffer models for i/v characteristics. table 10. processor agtl bus specifications symbol parameter min typ max units notes v tt bus termination voltage 1.1375 1.25 1.3625 v 1, 2 on-die r tt termination resistor 56 68 ? 1, 3 v ref bus reference voltage 2/3v tt v1, 4 notes: 1. the lv intel pentium iii processor 512k contains agtl termination resistors on the processor die, except for the reset# input. 2. v tt must be held to 1.25v 9%. it is required that v tt be held to 1.25v 3% while the processor system bus is idle (static condition). this is measured at the package ball on the micro-fcbga part. 3. uni-processor platforms require a 56 ? resistor and dual-processor platforms require a 68 ? resistor. tolerance for on-die rtt is +/-10% . 4. v ref is generated on the motherboard and should be 2/3 v tt 5% nominally. ensure that there is adequate v ref decoupling on the motherboard.
lv intel ? pentium ? iii processor 512k datasheet 29 table 11. clkref, apic, tap, cmos, and open-drain signal group dc specifications symbol parameter min max unit notes v il15 input low voltage, 1.5 v cmos ? 0.15 v cmos_refmin ? 300 mv v v il18 input low voltage, 1.8 v cmos ? 0.36 0.36 v 1 v ih15 input high voltage, 1.5 v cmos v cmos_refmax + 250 mv 1.65 v 10 v ih15picd input high voltage, 1.5 v picd[1:0] v cmos_refmax + 200 mv 1.65 v 11 v ih18 input high voltage, 1.8 v cmos 1.44 2.0 v 1 v oh15 output high voltage, 1.5 v cmos n/a 1.615 v 12 v oh33 output high voltage, 3.3 v signals 2.0 3.465 v 9 v ol33 output low voltage, 3.3 v signals 0.8 v v ol output low voltage 0.3 v 7 v cmos_ref cmosref voltage 0.90 1.10 v 3 v clkref clkref voltage 1.187 1.312 v 8 v ilvttpwr input low voltage, vtt_pwrgd 0.4 v 6 v ihvttpwr input high voltage, vtt_pwrgd 1.033 v 6 r on 30 ? 2 i ol output low current 10 ma 5 i l leakage current for inputs, outputs and i/os 100 a 4 notes: 1. this parameter applies to the non-agtl signal pwrgood. 2. this value was measured at 9 ma. 3. v cmos_ref should be created from a stable voltage supply (1.5 v or 1.8 v) using a voltage divider. it must track the voltage supply to maintain noise immunity. 4. (0 v in/out v ihx,max ) 5. specified as the minimum amount of current that the output buffer must be able to sink. however, v ol,max cannot be guaranteed if this specification is exceeded. 6. this parameter applies to vtt_pwrgd signal only. 7. this applies to non-agtl signal picclk. 8. 5% dc tolerance. clkref must be generated from a stable source. ac tolerance must be < -40db @ 1 mhz. 9. this applies to non-agtl signals vid[3:0, 25mv] and bsel[1:0]. 10.this applies to all tap and cmos signals (not to apic signals). 11.this applies to picd[1:0]. 12.all outputs are open-drain.
lv intel ? pentium ? iii processor 512k 30 datasheet 3.11 ac specifications 3.11.1 system bus, clock, apic, tap, cmos, and open-drain ac specifications the processor system bus timings specified in this section are defined at the processor core (pads). all system bus ac specifications for the agtl signal group are relative to the crossing point of the rising edge of the bclk input and falling edge of the bclk# input. all agtl timings are referenced to v ref for both ?0? and ?1? logic levels unless otherwise specified. all apic, tap, cmos, and open-drain signals except pwrgood are referenced to 1.0 v. all minimum and maximum specifications are at points within the power supply ranges shown in table 6 and junction temperatures (tj) in the range 0 c to 100 c. tj must be less than or equal to 100 c for all functional processor states. table 12. system bus clock ac specifications (differential) symbol parameter min typ max unit figure notes 1 system bus frequency 133 mhz t1 bclk period - average 7.5 7.7 ns 12 2 t1abs bclk period ? instantaneous minimum 7.3 ns 2 t2 bclk cycle to cycle jitter 200 ps 2 , 3 , 4 t5 bclk rise time 175 467 ps 12 2 , 6 t6 bclk fall time 175 467 ps 12 2 , 6 vcross for 1 v swing 0.51 0.76 v 11 7 rise/fall time matching 325 ps 5 bclk duty cycle 45% 55% 2 notes: 1. all ac timings for agtl and cmos signals are referenced to the bclk and bclk# crossing point. 2. measured on differential waveform: defined as (bclk - bclk#). 3. not 100% tested. specified by design/characterization. 4. due to the difficulty of accurately measuring clock jitter in a system, it is recommended that the clock driver be designed to meet a period stability specification into a test load of 10 to 20 pf. this should be measured on the rising edge of adjacent bclks at the bclk and bclk# crossing point. the jitter present must be accounted for as a component of bclk skew between devices. period difference is measured around 0 v crossing points. 5. measurement taken from common mode waveform. measure rise/fall time from 0.41 to 0.86 v. rise/fall time matching is defined as ?the instantaneous difference between maximum bclk rise (fall) and minimum bclk# fall (rise) time, or minimum bclk rise (fall) and maximum bclk# fall (rise) time?. this parameter is designed to guard waveform symmetry. 6. rise time is measured from -0.35 v to 0.35 v and fall time is measured from 0.35 v to -0.35 v. 7. measured on common mode waveform - includes every rise/fall crossing.
lv intel ? pentium ? iii processor 512k datasheet 31 table 13. system bus clock ac specifications (133 mhz, single-ended) symbol parameter min max unit figure notes 1 system bus frequency 133 mhz t1s bclk period 7.5 7.65 ns 10 2 t1sabs bclk period ? instantaneous minimum 7.25 2 t2s bclk period stability 250 ps 2 , 3 , 4 t3s bclk high time 1.4 ns 10 6 t4s bclk low time 1.4 ns 10 7 t5s bclk rise time 0.4 1.6 ns 10 5 t6s bclk fall time 0.4 1.6 ns 10 5 notes: 1. all ac timings for gtl+ and cmos signals are referenced to the bclk rising edge at 1.25 v. 2. period, jitter, skew and offset measured at 1.25 v. 3. not 100% tested. specified by design/characterization. 4. measured on the rising edge of adjacent bclks at 1.25 v. the jitter present must be accounted for as a component of bclk skew between devices. 5. measured between 0.5 v and 2.0 v 6. measured when the bclk signal voltage level is above 2.0 v 7. measured when the bclk signal voltage level is below 0.5 v
lv intel ? pentium ? iii processor 512k 32 datasheet table 14. valid lv intel pentium iii processor 512k frequencies bclk frequency (mhz) frequency multiplier core frequency (mhz) power-on configuration bits [27,25:22] 133 6 800 0, 1011 133 7 933 0, 1100 133 8 1000 0, 1101 note: while other combinations of bus and core frequencies are defined, operation at frequencies other than those listed above will not be validated by intel and are not guaranteed. the frequency multiplier is programmed into the processor when it is manufactured and it cannot be changed. table 15. agtl signal groups ac specifications r tt internally terminated to v tt ; v ref = 2 / 3 v tt ; load = 50 ? symbol parameter min max unit figure notes 1 t7 agtl output valid delay 0.40 3.25 ns 13 t8 agtl input setup time 0.95 ns 14 2 , 3 t9 agtl input hold time 1 ns 14 4 t10 reset# pulse width 1 ms 15 , 16 5 notes: 1. all ac timings for agtl signals are referenced to the crossing point of the bclk rising edge and the bclk# falling edge for differential clocking and to the bclk rising edge at 1.25 v for single-ended clocking. all agtl signals are referenced at v ref . 2. reset# can be asserted (active) asynchronously, but must be de-asserted synchronously. 3. this specification is for a minimum 0.40 v swing from v ref ? 200 mv to v ref +200 mv. 4. this specification is for a maximum 0.80 v swing from v tt ? 0.8 v to v tt . 5. valid after v cc core , v tt , and bclk, bclk# become stable and pwrgood is asserted. table 16. cmos and open-drain signal groups ac specifications symbol parameter min max unit figure notes 1, 2 t14 1.5 v input pulse width, except pwrgood and lint[1:0] 2bclks 15 5 t14b lint[1:0] input pulse width 6 bclks 15 3 t15 pwrgood inactive pulse width 2 s 16 4 notes: 1. all ac timings for cmos and open-drain signals are referenced to the crossing point of the bclk rising edge and bclk# falling edge for differential clocking and to the rising edge of bclk at 1.25 v for single- ended clocking. all cmos and open-drain signals are referenced at 1.0 v. 2. minimum output pulse width on cmos outputs is two bclks. 3. this specification only applies when the apic is enabled and the lint1 or lint0 signal is configured as an edge triggered interrupt with fixed delivery, otherwise specification t14 applies. 4. when driven inactive, or after v cc core , v tt and bclk, bclk# become stable. pwrgood must remain below v il18,max until all the voltage planes meet the voltage tolerance specifications in table 9 and bclk, bclk# have met the bclk, bclk# ac specifications in table 20 and table 21 for at least 2 s. pwrgood must rise error-free and monotonically to 1.8 v. 5. for active and inactive states
lv intel ? pentium ? iii processor 512k datasheet 33 table 17. reset configuration ac specifications and power on timings symbol parameter min typ max unit figure notes t16 reset configuration signals (a[15:5]#, br0#, flush#, init#, picd0) setup time 4bclks 15 1 t17 reset configuration signals (a[15:5]#, br0#, flush#, init#, picd0) hold time 220bclks 15 2 t18 reset#/pwrgood setup time 1 ms 16 1, 3 t18a v tt to vtt_pwrgd setup time 1 ms 16 t18b v cc core to pwrgood setup time 10 ms 16 t18c bsel, vid valid time before vtt_pwrgd assertion 1 s 16 t18d reset# inactive to valid outputs 1 bclk 15 t18e reset# inactive to drive signals 4 bclks 15 note: 1. applies before deassertion of reset# 2. applies after clock that deasserts reset# 3. at least 1 ms must pass after pwrgood rises above v ih18min and bclk, bclk# meet their ac timing specification until reset# may be deasserted. table 18. apic bus signal ac specifications symbol parameter min max unit figure notes 1 t21 picclk frequency 2 33.3 mhz 2 t22 picclk period 30 500 ns 10 t23 picclk high time 10.5 ns 10 5 t24 picclk low time 10.5 ns 10 6 t25 picclk rise time 0.25 3.0 ns 10 7 t26 picclk fall time 0.25 3.0 ns 10 8 t27 picd[1:0] setup time 8.0 ns 13 3 t28 picd[1:0] hold time 2.5 ns 13 3 t29 picd[1:0] valid delay (rising edge) picd[1:0] valid delay (falling edge) 1.5 1.5 8.7 12.0 ns 12 3 , 4 notes: 1. all ac timings for apic signals are referenced to the picclk rising edge at 1.0 v. all cmos signals are referenced at 1.0 v. 2. the minimum frequency is 2 mhz when picd0 is at 1.5 v at reset referenced to picclk rising edge. 3. for open-drain signals, valid delay is synonymous with float delay. 4. valid delay timings for these signals are specified into 150 ? to 1.5 v and 0 pf of external load. for real system timings these specifications must be derated for external capacitance at 105 ps/pf. 5. measured when the picclk signal voltage level is above 1.6 v 6. measured when the picclk signal voltage level is below 1.6 v 7. measured from 0.4 v to 1.6 v 8. measured from 1.6 v to 0.4 v
lv intel ? pentium ? iii processor 512k 34 datasheet table 19. tap signal ac specifications symbol parameter min max unit figure notes 1 t30 tck frequency ? 16.67 mhz t31 tck period 60 ? ns 10 t32 tck high time 25.0 ns 10 2 , 9 t33 tck low time 25.0 ns 10 2 , 10 t34 tck rise time 5.0 ns 10 2 , 3 , 11 t35 tck fall time 5.0 ns 10 2 , 3 , 12 t36 trst# pulse width 40.0 ns 18 2 t37 tdi, tms setup time 5.0 ns 17 4 t38 tdi, tms hold time 14.0 ns 17 4 t39 tdo valid delay 1.0 10.0 ns 17 5 , 6 t40 tdo float delay 25.0 ns 17 2 , 5 , 6 t41 all non-test outputs valid delay 2.0 25.0 ns 17 5 , 7 , 8 t42 all non-test outputs float delay 25.0 ns 17 2 , 5 , 7 , 8 t43 all non-test inputs setup time 5.0 ns 17 4 , 7 , 8 t44 all non-test inputs hold time 13.0 ns 17 4 , 7 , 8 notes: 1. all ac timings for tap signals are referenced to the tck rising edge at 1.0 v. all tap and cmos signals are referenced at 1.0 v. 2. not 100% tested. specified by design/characterization. 3. 1 ns can be added to the maximum tck rise and fall times for every 1 mhz below 16 mhz. 4. referenced to tck rising edge 5. referenced to tck falling edge 6. valid delay timing for this signal is specified into 150 ? terminated to 1.5 v and 0 pf of external load. for real system timings these specifications must be derated for external capacitance at 105 ps/pf. 7. non-test outputs and inputs are the normal output or input signals (except tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to boundary scan operations. 8. during debug port operation use the normal specified timings rather than the tap signal timings. 9. measured when the tck signal voltage level is at or above v cmos_ref + 0.2 v. 10.measured when the tck signal voltage level is at or below v cmos_ref - 0.2 v. 11.measured from v cmos_ref - 0.2 v to v cmos_ref + 0.2 v 12.measured from v cmos_ref + 0.2 v to v cmos_ref - 0.2 v
lv intel ? pentium ? iii processor 512k datasheet 35 figure 10. bclk (single ended)/picclk/tck generic clock timing waveform notes: t r = t5s, t5s1, t34, t25 (rise time) t f = t6s, t6s1, t35, t26 (fall time) t h = t3s, t3s1, t32, t23 (high time) t l = t4s, t4s1, t33, t24 (low time) t p = t1s, t1s1, t31, t22 (period) v trip = 1.25 v for bclk (single ended);1.0 v for picclk; 1.0 v for tck v l = 0.5 v for bclk (single ended);0.4 v for picclk; (v cmos_ref -0.2 v) for tck v h = 2.0 v for bclk (single ended);1.6 v for picclk; (v cmos_ref +0.2 v) for tck figure 11. differential bclk/bclk# waveform (common mode) clk v h v l v trip t h t l t p t r t f d0003-01 bclk bclk# vcross v2,v3 (max) v1,v3 (min)
lv intel ? pentium ? iii processor 512k 36 datasheet figure 12. bclk/bclk# waveform (differential mode) figure 13. valid delay timings notes: t x = t7, t11, t29 (valid delay) t pw = t14, t14b (pulse width) v = v ref for agtl signal group; 1.0 v for cmos, open-drain, apic, and tap signal groups vc = crossing point of bclk rising edge and bclk# falling edge for bclk references (differential clock) = 1.25 v (single-ended clock) 0v t6 t5 t1 v4 v5 v ih_diff v il_diff clk signal t x t x t pw v valid valid d0004-00 vc vc
lv intel ? pentium ? iii processor 512k datasheet 37 figure 14. setup and hold timings notes: t s = t 8, t12, t27 (setup time) t h = t9, t13, t28 (hold time) v = v ref for agtl signals; 1.0 v for cmos, apic, and tap signals vc = crossing point of bclk rising edge and bclk# falling edge for bclk references (differential clock) = 1.25 v (single-ended clock) figure 15. cold/warm reset and configuration timings notes: t t = t9 (agtl input hold time) t u = t8 (agtl input setup time) t v = t10 (reset# pulse width) t w = t16 (reset configuration signals (a[15:5]#, br0#, flush#, init#, picd0) setup time) t x = t17 (reset configuration signals (a[15:5]#, br0#, flush#, init#, picd0) hold time) t y = t18d (reset# inactive to valid outputs) t z = t18e (reset# inactive to drive signals) vc = crossing point of bclk rising edge and bclk# falling edge (differential clock) = 1.25 v (single-ended clock) clk signal v valid t h ts d0005-00 vc bclk reset# t v t x t t t u v c v d0006-02 configuration (a[15:5], breq0#, flush#, init#, picd0) t w valid picd[1:0] agtl/non-agtl outputs non-configuration inputs t y valid t z active (a[15:5],br0#
lv intel ? pentium ? iii processor 512k 38 datasheet figure 16. power-on sequence and reset timings notes: t a = t15 (pwrgood inactive pulse width) t b = t18 (reset#/pwrgood setup time) t c = t18b (setup time from v cc core valid until pwrgood assertion) t d = t18a (setup time from v tt valid to vtt_pwrgd assertion) t e = t18c(vid, bsel valid time before vtt_pwrgd assertion) v cct valid vttpwrgd vid[4:0]/ bsel[1:0] cmosref/ clkref/v ref pwrgood reset# bclk/bclk# v ih18,min v il18,max v ihvttpw r,min v ilvttpw r,max t a t c t b v cc v0040-00 t e t d vtt_pwrgd vid[3:0, 25mv]/ v cmos_ref v tt v cc core
lv intel ? pentium ? iii processor 512k datasheet 39 figure 17. test timings (boundary scan) notes: t r = t43 (all non-test inputs setup time) t s = t44 (all non-test inputs hold time) t u = t40 (tdo float delay) t v = t37 (tdi, tms setup time) t w = t38 (tdi, tms hold time) t x = t39 (tdo valid delay) t y = t41 (all non-test outputs valid delay) t z = t42 (all non-test outputs float delay) figure 18. test reset timings note: t q = t36 (trst# pulse width) tck tdi, tms input signals tdo output signals 0.75v t v t w t r t s t x t u t y t z d0008-01 trst# 0.75v t q d0009-01
lv intel ? pentium ? iii processor 512k 40 datasheet 4.0 system signal simulations systems must be simulated using the lv intel pentium iii processor 512k ibis models to determine if they are compliant with this specification. all references to bclk signal quality also apply to bclk# for differential clocking. 4.1 s ystem bus clock (bclk) and picclk dc specifications and ac signal quality specifications table 20. bclk (differential) dc specifications and ac signal quality specifications symbol parameter min max unit figure notes v1 v il,bclk -0.2 0.35 v 11 1 v2 v ih,bclk 0.92 1.45 v 11 1 v3 v in absolute voltage range -0.2 1.45 v 11 2 , 4 v4 bclk rising edge ringback 0.35 v 12 3 v5 bclk falling edge ringback -0.35 v 12 3 notes: 1. the clock must rise/fall monotonically between vil,bclk and vih,bclk. 2. these specifications apply only when bclk, bclk# are running. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) voltage the differential waveform can go to after passing the vih_diff (rising) or vil_diff (falling) levels. 4. for undershoot and overshoot table 21. bclk (single-ended) dc specifications and ac signal quality specifications symbol parameter min max unit figure notes v1 v il,bclk 0.3 v 19 1 v2 v ih,bclk 2.2 v 19 1 v3 v in absolute voltage range -0.5 3.1 v 19 2 , 4 v4 bclk rising edge ringback 2.0 v 19 3 , 5 v5 bclk falling edge ringback 0.5 v 19 3 , 5 notes: 1. the clock must rise/fall monotonically between v il,bclk and v ih,bclk . bclk must be stopped in the low state. 2. these specifications apply only when bclk is running. bclk may not be above v ih,bclk,max or below v il, bclk,min for more than 50% of the clock cycle. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can go to after passing the v ih,bclk (rising) or v il,bclk (falling) voltage limits. 4. for overshoot and undershoot. 5. absolute value
lv intel ? pentium ? iii processor 512k datasheet 41 table 22. picclk dc specifications and ac signal quality specifications symbol parameter min max unit figure notes v1 v il20 0.4 v 19 1 v2 v ih20 1.6 v 19 1 v3 v in absolute voltage range -0.4 2.4 v 19 2 , 4 v4 picclk rising edge ringback 1.6 v 19 3 , 5 v5 picclk falling edge ringback 0.4 v 19 3 , 5 notes: 1. the clock must rise/fall monotonically between v il20 and v ih20 . 2. these specifications apply only when picclk is running. see the dc specifications for when picclk is stopped. picclk may not be above v ih20,max or below v il20,min for more than 50% of the clock cycle. 3. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the picclk signal can go to after passing the v ih20 (rising) or v il20 (falling) voltage limits. 4. for overshoot and undershoot 5. absolute value figure 19. bclk (single-ended)/picclk generic clock waveform v0012-01 v1 v2 v3 max v4 v3 min v5
lv intel ? pentium ? iii processor 512k 42 datasheet 4.2 agtl ac signal quality specifications the ringback specifications for the agtl signals are as follows: ? ringback below v ref,max + 200 mv is not authorized during low to high transitions. ? ringback above v ref,min ? 200 mv is not authorized during high to low transitions. overshoot and undershoot specifications are documented in table 23 and illustrated in figure 20 . figure 20. maximum acceptable overshoot/undershoot waveform max vss time dependent overshoot time dependent undershoot min
lv intel ? pentium ? iii processor 512k datasheet 43 4.3 non-agtl signal quality specifications signals driven to the lv intel pentium iii processor 512k should meet signal quality specifications to ensure that the processor reads data properly and that incoming signals do not affect the long- term reliability of the processor. the overshoot and undershoot specifications for non agtl signals are shown in table 24 . table 23. 133 mhz agtl signal group overshoot/undershoot tolerance at the processor core max v tt + overshoot/undershoot magnitude (volts) allowed pulse duration (ns) [t j =100 c] activity factor = 0.01 activity factor = 0.1 activity factor = 1 1.78 1.5 0.15 0.015 1.73 3.5 0.35 0.035 1.68 7.2 0.72 0.072 1.63 15 1.5 0.15 1.58 15 3.2 0.32 1.53 15 6.5 0.65 1.48 15 14 1.40 notes: 1. under no circumstances should the sum of the max v tt and absolute value of the overshoot/undershoot voltage exceed 1.78 v. 2. activity factor of 1 represents the same toggle rate as the 133-mhz clock. 3. ringbacks below v tt cannot be subtracted from overshoots. lesser undershoot does not allocate longer or larger overshoot. 4. ringbacks above ground cannot be subtracted from undershoots. lesser overshoot does not allocate longer or larger undershoot. 5. system designers are encouraged to follow intel provided agtl layout guidelines. 6. all values are specified by design characterization and are not tested. table 24. non-agtl signal group overshoot/undershoot tolerance at the processor core max v cmos + overshoot/undershoot magnitude (volts) allowed pulse duration (ns) [tj=100 c] activity factor = 0.01 activity factor = 0.1 activity factor = 1 2.38 6.5 0.65 0.065 2.33 13 1.3 0.13 2.28 29 2.9 0.29 2.23 60 6 0.6 2.18 60 12 1.2 2.13 60 26 2.6 2.08 60 56 5.6 notes: 1. v cmos (nominal) = 1.5 v 2. under no circumstances should the sum of the max v cmos and absolute value of the overshoot/ undershoot voltage exceed 2.38 v. 3. activity factor of 1 represents a toggle rate of 33 mhz 4. system designers are encouraged to follow intel provided non-agtl layout guidelines. 5. all values are specified by design characterization, and are not tested.
lv intel ? pentium ? iii processor 512k 44 datasheet 4.3.1 pwrgood signal quality specification the processor requires pwrgood to be a clean indication that clocks and the power supplies (v cc core , v tt , etc.) are stable and within their specifications. clean implies that the signal will remain below v il18 and without errors from the time that the power supplies are turned on, until they come within specification. the signal will then transition monotonically to a high (1.8 v) state. 4.3.2 vtt_pwrgd signal quality specification the vtt_pwrgd signal is an input to the processor that is used to determine that the v tt power is stable and that the vid and bsel signals should be driven to their final states by the processor. to ensure the processor correctly reads this signal, it must meet the following requirement while the signal is in its transition region of 300 mv to 900 mv: vtt_pwrgd should only enter the transition region once, after v tt is at nominal voltage, for the assertion of the signal. in addition, the vtt_pwrgd signal should have reasonable transition time through the transition region. a sharp edge on the signal transition minimizes the chance of noise causing a glitch on this signal. intel recommends the following transition time for the vtt_pwrgd signal: 4.3.2.1 transition region the transition region covered by this requirement is 300 mv to 900 mv. once the vtt_pwrgd signal is in that voltage range, the processor is more sensitive to noise that may be present on the signal. the transition region begins when the signal first crosses the 300 mv voltage level and ends before the signal crosses 900 mv. 4.3.2.2 transition time the transition time is defined as the time the signal takes to move through the transition region. a 100 s transition time ensures that the processor receives a good transition edge. 4.3.2.3 noise the signal quality of the vtt_pwrgd signal is critical to the correct operation of the processor. every effort should be made to ensure this signal is monotonic in the transition region. if noise or glitches are present on this signal, it must be kept to less than 100 mv of a voltage drop from the highest voltage level received to that point. this glitch must remain less than 100 mv until the excursion ends. the excursion ends when the voltage returns to the highest voltage previously received. figure 21 provides an example graph of this situation and requirements. parameter specification amount of noise (glitch) less than 100 mv parameter specification transition time (300 mv to 900 mv) less than or equal to 100 s
lv intel ? pentium ? iii processor 512k datasheet 45 figure 21. noise estimation transition region microseconds
lv intel ? pentium ? iii processor 512k 46 datasheet 5.0 mechanical specifications 5.1 surface mount micro-fcbga package the lv intel pentium iii processor 512k is available in a surface mount, 479-ball micro-fcbga package. mechanical specifications are shown in table 25 . figure 22 through figure 25 illustrate different views of the package. the micro-fcbga package may have capacitors placed in the area surrounding the die. because the die-side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid placing the capacitors in contact with electrically conductive materials. doing so may short the capacitors, and can damage the device or render it inactive. consider using an insulating material between the capacitors and the thermal solution to prevent shorting the capacitor. note: all dimensions are in millimeters. values shown are for reference only. table 25. micro-fcbga package mechanical specifications symbol parameter min max unit a overall height, as delivered (1) 2.27 2.77 mm a2 die height 0.854 mm b ball diameter 0.78 mm d package substrate length 34.9 35.1 mm e package substrate width 34.9 35.1 mm d1 die length 11.18 mm e1 die width 7.19 mm e ball pitch 1.27 mm n ball count 479 each k keep-out outline from edge of package 5 mm k1 keep-out outline at corner of package 7 mm k2 capacitor keep-out height ? 0.7 mm s package edge to first ball center 1.625 mm -- solder ball coplanarity 0.2 mm pdie allowable pressure on the die for thermal solution ? 689 kpa w package weight 4.5 g notes: 1. all dimensions are subject to change. 2. overall height as delivered. values were based on design specifications and tolerances. final height after surface mount depends on oem motherboard design and smt process.
lv intel ? pentium ? iii processor 512k datasheet 47 figure 22. micro-fcbga package ? top and bottom isometric views top view bottom view label die package keepout capacitor area
lv intel ? pentium ? iii processor 512k 48 datasheet figure 23. micro-fcbga package ? top and side views 35 (e) 35 (d) ball a1 corner e1 d1 a ?0.78 (b) 479 places k2 substrate keepout zone do not contact package inside this line 7 (k1) 8 places 5 (k) 4 places note: all dimensions in millimeters. values shown are for reference a2 0.20
lv intel ? pentium ? iii processor 512k datasheet 49 figure 24. micro-fcbga package - bottom view 1 2 3 4 6 8 1012141618 20 22 24 26 57911 13 15 17 19 21 23 25 a b c e d f g h j k l m n p r t u v w y a a ab ac ad ae af note: all dimensions in millimeters. values shown are for reference only 25x 1.27 (e) 25x 1.27 (e) 1.625 (s) 4 places 1.625 (s) 4 places
lv intel ? pentium ? iii processor 512k 50 datasheet 5.2 signal listings figure 22 is a top-side view of the ball map of the lv intel pentium iii processor 512k with the voltage balls called out. table 26 lists the signals in ball number order. table 27 lists the signals in signal name order. figure 25. ball map - top view a10# vref nc a31# br0# br1# a23# a27# a24# nc a35# a26# a33# a32# d0# d2# d15# d9# d7# vref d8# d10# d11# vss vtt nc vss a25# vss a17# vss a21# vss a20# vss a18# vss a34# vss reset# vss d1# vss d4# vss d17# vss d18# d14# d24# vss nc a16# a28# vtt a19# vtt a22# vtt a30# vtt a29# vtt berr# vtt d6# vtt d12# vtt d5# vtt nc vss d20# vss d30# nc vss a13# vss vtt vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vcccore vss vss vss vss vss vss vss vss d3# d13# d22# nc nc testhi vtt vtt vss vss vss vss vss vss vss vss d16# d23# vss d19# nc vss a14# vss vss vss vss vss vss vss vss vss vss vss d21# d36# d27# a9# a5# a15# vtt vss vss vtt d25# vss d32# a12# vss a8# vss vss vss vss d26# d29# vref a4# a7# a11# vtt vss vss vtt d34# vss d38# a3# vss a6# vss vss vss vss d31# d33# d35# req4# bnr# req1# vtt ghi# vss vss vtt d28# vss d42# vss vss vss rsp# vss vss d39# d45# d48# vref pll2 pll1 nc vss vss vtt nc vss d37# nc vss api# nc nc nc vss vss d49# d41# nc req0# bpri# vid4 vss vss vss vtt d43# vss d44# req2# vss defer# rp# vss vss vss d47# d57# d51# req3# hitm# rs2# vss vss vss vtt d52# vss d40# rs1# vss lock# vtt vss vss vss d63# d46# d55# trdy# aerr# dbsy# vss vss vss vtt d59# vss d54# drdy# vss rs0# vss vss vss d58# d53# d60# vref hit# ads# vtt vss vss vss vss vss vss vss vss vss vtt d62# vss d50# vid0 vss ap0# pwr good vss vss vss vss vss vss vss vss vss vss d61# d56# vref bclk vid1 a20m# vtt vss vss vss vss vss vss vss vss vss vtt dep3# vss dep6# bclk# / clkref vss smi# _ref vcmos _ref vcmos vtt tdi vtt ignne# tck therm tdo vtt nc vtt lint0 picd1 vtt picd0 vtt bpm1# bpm0# nc dep7# dep1# dep5# vss vid2 vtt stpclk# vss init# vss nc vss vss trip# bsel0 vss lint1 vss vss vtt vss bp3# vss prdy# vss dep0# dep2# vss vtt vtt vid3 ierr# flush# ferr# slp# tms vref bsel1 testhi trst# thermdp thermdn nc nch ctrl rtt ctrl slew ctrl nc preq# picclk vref bp2# binit# dep4# vss vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 vtt_ pwrgd a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1234567891011121314151617181920212223242526 vcccore vss other vtt testlo testlo nc nc vid25mv
mechanical specifications datasheet 51 table 26. signal list by ball number no. signal name a2 nc a3 a10# a4 vref a5 nc a6 a31# a7 br0# a8 a23# a9 a27# a10 a24# a11 nc a12 a35# a13 a26# a14 a33# a15 a32# a16 d0# a17 d2# a18 d15# a19 d9# a20 d7# a21 vref a22 d8# a23 d10# a24 d11# a25 vss a26 vtt b1 nc b2 vss b3 a25# b4 vss b5 a17# b6 vss b7 a21# b8 vss b9 a20# b10 vss b11 a18# b12 vss b13 a34# b14 vss b15 reset# b16 vss b17 d1# b18 vss b19 d4# b20 vss b21 d17# b22 vss b23 d18# b24 d14# b25 d24# b26 vss c1 nc c2 a16# c3 a28# c4 br1# c5 vtt c6 a19# c7 vtt c8 a22# c9 vtt c10 a30# c11 vtt c12 a29# c13 vtt c14 berr# c15 vtt c16 d6# c17 vtt c18 d12# c19 vtt c20 d5# c21 vtt c22 nc c23 vss c24 d20# c25 vss c26 d30# d1 nc d2 vss d3 a13# d4 vss d5 vtt table 26. signal list by ball number no. signal name d6 vcccore d7 vss d8 vcccore d9 vss d10 vcccore d11 vss d12 vcccore d13 vss d14 vcccore d15 vss d16 vcccore d17 vss d18 vcccore d19 vss d20 vcccore d21 vss d22 vcccore d23 d3# d24 d13# d25 d22# d26 nc e1 nc e2 testhi e3 vtt_pwrgd e4 vtt e5 vcccore e6 vtt e7 vcccore e8 vss e9 vcccore e10 vss e11 vcccore e12 vss e13 vcccore e14 vss e15 vcccore e16 vss e17 vcccore e18 vss e19 vcccore e20 vss table 26. signal list by ball number no. signal name e21 vcccore e22 vss e23 d16# e24 d23# e25 vss e26 d19# f1 nc f2 vss f3 a14# f4 vss f5 vss f6 vcccore f7 vss f8 vcccore f9 vss f10 vcccore f11 vss f12 vcccore f13 vss f14 vcccore f15 vss f16 vcccore f17 vss f18 vcccore f19 vss f20 vcccore f21 vss f22 vcccore f23 vss f24 d21# f25 d36# f26 d27# g1 a9# g2 a5# g3 a15# g4 vtt g5 vcccore g6 vss g21 vcccore g22 vss g23 vtt table 26. signal list by ball number no. signal name
mechanical specifications 52 datasheet g24 d25# g25 vss g26 d32# h1 a12# h2 vss h3 a8# h4 vss h5 vss h6 vcccore h21 vss h22 vcccore h23 vss h24 d26# h25 d29# h26 vref j1 a4# j2 a7# j3 a11# j4 vtt j5 vcccore j6 vss j21 vcccore j22 vss j23 vtt j24 d34# j25 vss j26 d38# k1 a3# k2 vss k3 a6# k4 vss k5 vss k6 vcccore k21 vss k22 vcccore k23 vss k24 d31# k25 d33# k26 d35# l1 req4# l2 bnr# table 26. signal list by ball number no. signal name l3 req1# l4 vtt l5 nc l6 vss l21 vcccore l22 vss l23 vtt l24 d28# l25 vss l26 d42# m1 testlo m2 vss m3 vss m4 vss m5 rsp# m6 vcccore m21 vss m22 vcccore m23 vss m24 d39# m25 d45# m26 d48# n1 vref n2 pll2 n3 pll1 n4 nc n5 vcccore n6 vss n21 vcccore n22 vss n23 vtt n24 nc n25 vss n26 d37# p1 nc p2 vss p3 ap1# p4 nc p5 nc p6 vcccore p21 vss table 26. signal list by ball number no. signal name p22 vcccore p23 vss p24 d49# p25 d41# p26 nc r1 req0# r2 bpri# r3 vid25mv r4 vss r5 vcccore r6 vss r21 vcccore r22 vss r23 vtt r24 d43# r25 vss r26 d44# t1 req2# t2 vss t3 defer# t4 rp# t5 vss t6 vcccore t21 vss t22 vcccore t23 vss t24 d47# t25 d57# t26 d51# u1 req3# u2 hitm# u3 rs2# u4 vss u5 vcccore u6 vss u21 vcccore u22 vss u23 vtt u24 d52# u25 vss u26 d40# table 26. signal list by ball number no. signal name v1 rs1# v2 vss v3 lock# v4 vtt v5 vss v6 vcccore v21 vss v22 vcccore v23 vss v24 d63# v25 d46# v26 d55# w1 trdy# w2 aerr# w3 dbsy# w4 vss w5 vcccore w6 vss w21 vcccore w22 vss w23 vtt w24 d59# w25 vss w26 d54# y1 drdy# y2 vss y3 rs0# y4 testlo y5 vss y6 vcccore y21 vss y22 vcccore y23 vss y24 d58# y25 d53# y26 d60# aa1 vref aa2 hit# aa3 ads# aa4 vtt aa5 vcccore table 26. signal list by ball number no. signal name
mechanical specifications datasheet 53 aa6 vss aa7 vcccore aa8 vss aa9 vcccore aa10 vss aa11 vcccore aa12 vss aa13 vcccore aa14 vss aa15 vcccore aa16 vss aa17 vcccore aa18 vss aa19 vcccore aa20 vss aa21 vcccore aa22 vss aa23 vtt aa24 d62# aa25 vss aa26 d50# ab1 vid0 ab2 vss ab3 ap0# ab4 pwrgood ab5 vss ab6 vcccore ab7 vss ab8 vcccore ab9 vss ab10 vcccore ab11 vss ab12 vcccore ab13 vss ab14 vcccore ab15 vss ab16 vcccore ab17 vss ab18 vcccore ab19 vss ab20 vcccore table 26. signal list by ball number no. signal name ab21 vss ab22 vcccore ab23 vss ab24 d61# ab25 d56# ab26 vref ac1 bclk ac2 vid1 ac3 a20m# ac4 vtt ac5 vcccore ac6 vss ac7 vcccore ac8 vss ac9 vcccore ac10 vss ac11 vcccore ac12 vss ac13 vcccore ac14 vss ac15 vcccore ac16 vss ac17 vcccore ac18 vss ac19 vcccore ac20 vss ac21 vcccore ac22 vss ac23 vtt ac24 dep3# ac25 vss ac26 dep6# ad1 bclk#/ clkref ad2 vss ad3 smi# ad4 nc ad5 vcmos_ref ad6 vtt ad7 tdi ad8 vtt table 26. signal list by ball number no. signal name ad9 ignne# ad10 tck ad11 tdo ad12 vtt ad13 nc ad14 vtt ad15 lint0 ad16 nchctrl ad17 picd1 ad18 vtt ad19 picd0 ad20 vtt ad21 bpm1# ad22 bpm0# ad23 nc ad24 dep7# ad25 dep1# ad26 dep5# ae1 vss ae2 vid2 ae3 vtt ae4 stpclk# ae5 vss ae6 init# ae7 vss ae8 nc ae9 vss ae10 thermtrip# ae11 vss ae12 bsel0 ae13 vss ae14 lint1 ae15 vss ae16 rttctrl ae17 vss ae18 vtt ae19 vss ae20 bp3# ae21 vss ae22 prdy# ae23 vss table 26. signal list by ball number no. signal name ae24 dep0# ae25 dep2# ae26 vss af1 vtt af2 vtt af3 vid3 af4 ierr# af5 flush# af6 ferr# af7 tms af8 slp# af9 vref af10 bsel1 af11 testhi af12 vcmos_ref af13 thermdp af14 thermdn af15 trst# af16 slewctrl af17 nc af18 nc af19 preq# af20 picclk af21 vref af22 bp2# af23 binit# af24 dep4# af25 vss af26 vss table 26. signal list by ball number no. signal name
mechanical specifications 54 datasheet table 27. signal listing by signal name no. signal name signal buffer type k1 a3# agtl i/o j1 a4# agtl i/o g2 a5# agtl i/o k3 a6# agtl i/o j2 a7# agtl i/o h3 a8# agtl i/o g1 a9# agtl i/o a3 a10# agtl i/o j3 a11# agtl i/o h1 a12# agtl i/o d3 a13# agtl i/o f3 a14# agtl i/o g3 a15# agtl i/o c2 a16# agtl i/o b5 a17# agtl i/o b11 a18# agtl i/o c6 a19# agtl i/o b9 a20# agtl i/o ac3 a20m# 1.5 v cmos input b7 a21# agtl i/o c8 a22# agtl i/o a8 a23# agtl i/o a10 a24# agtl i/o b3 a25# agtl i/o a13 a26# agtl i/o a9 a27# agtl i/o c3 a28# agtl i/o c12 a29# agtl i/o c10 a30# agtl i/o a6 a31# agtl i/o a15 a32# agtl i/o a14 a33# agtl i/o b13 a34# agtl i/o a12 a35# agtl i/o aa3 ads# agtl i/o w2 aerr# agtl i/o ab3 ap0# agtl i/o p3 ap1# agtl i/o ac1 bclk clock input ad1 bclk#/clkref clock input c14 berr# agtl i/o af23 binit# agtl i/o l2 bnr# agtl i/o af22 bp2# agtl i/o ae20 bp3# agtl i/o ad22 bpm0# agtl i/o ad21 bpm1# agtl i/o r2 bpri# agtl input a7 br0# agtl i/o c4 br1# agtl i/o ae12 bsel0 3.3 v cmos output af10 bsel1 3.3 v cmos output a16 d0# agtl i/o b17 d1# agtl i/o a17 d2# agtl i/o d23 d3# agtl i/o b19 d4# agtl i/o c20 d5# agtl i/o c16 d6# agtl i/o a20 d7# agtl i/o a22 d8# agtl i/o a19 d9# agtl i/o a23 d10# agtl i/o a24 d11# agtl i/o c18 d12# agtl i/o d24 d13# agtl i/o b24 d14# agtl i/o a18 d15# agtl i/o e23 d16# agtl i/o b21 d17# agtl i/o b23 d18# agtl i/o e26 d19# agtl i/o c24 d20# agtl i/o f24 d21# agtl i/o d25 d22# agtl i/o e24 d23# agtl i/o b25 d24# agtl i/o g24 d25# agtl i/o h24 d26# agtl i/o f26 d27# agtl i/o l24 d28# agtl i/o h25 d29# agtl i/o c26 d30# agtl i/o k24 d31# agtl i/o g26 d32# agtl i/o k25 d33# agtl i/o j24 d34# agtl i/o k26 d35# agtl i/o f25 d36# agtl i/o n26 d37# agtl i/o j26 d38# agtl i/o m24 d39# agtl i/o u26 d40# agtl i/o p25 d41# agtl i/o l26 d42# agtl i/o r24 d43# agtl i/o table 27. signal listing by signal name no. signal name signal buffer type
mechanical specifications datasheet 55 r26 d44# agtl i/o m25 d45# agtl i/o v25 d46# agtl i/o t24 d47# agtl i/o m26 d48# agtl i/o p24 d49# agtl i/o aa26 d50# agtl i/o t26 d51# agtl i/o u24 d52# agtl i/o y25 d53# agtl i/o w26 d54# agtl i/o v26 d55# agtl i/o ab25 d56# agtl i/o t25 d57# agtl i/o y24 d58# agtl i/o w24 d59# agtl i/o y26 d60# agtl i/o ab24 d61# agtl i/o aa24 d62# agtl i/o v24 d63# agtl i/o w3 dbsy# agtl i/o t3 defer# agtl input ae24 dep0# agtl i/o ad25 dep1# agtl i/o ae25 dep2# agtl i/o ac24 dep3# agtl i/o af24 dep4# agtl i/o ad26 dep5# agtl i/o ac26 dep6# agtl i/o ad24 dep7# agtl i/o y1 drdy# agtl i/o af6 ferr# 1.5 v open drain output af5 flush# 1.5 v cmos input aa2 hit# agtl i/o u2 hitm# agtl i/o af4 ierr# 1.5 v open drain output ad9 ignne# 1.5 v cmos input ae6 init# 1.5 v cmos input ad15 intr/lint0 1.5 v cmos input v3 lock# agtl i/o ad16 nchctrl agtl impedance control ae14 nmi/lint1 1.5 v cmos input af20 picclk 1.8 v apic clock input ad19 picd0 1.5 v open drain i/o ad17 picd1 1.5 v open drain i/o n3 pll1 pll analog voltage n2 pll2 pll analog voltage ae22 prdy# agtl output table 27. signal listing by signal name no. signal name signal buffer type af19 preq# 1.5 v cmos input ab4 pwrgood 1.8 v cmos input r1 req0# agtl i/o l3 req1# agtl i/o t1 req2# agtl i/o u1 req3# agtl i/o l1 req4# agtl i/o b15 reset# agtl input t4 rp# agtl i/o y3 rs0# agtl i/o v1 rs1# agtl i/o u3 rs2# agtl i/o m5 rsp# agtl input ae16 rttctrl agtl pull-up control af16 slewctrl agtl control af8 slp# 1.5 v cmos input ad3 smi# 1.5 v cmos input ae4 stpclk# 1.5 v cmos input ad10 tck 1.5 v jtag clock input ad7 tdi jtag input ad11 tdo jtag output e2 testhi test use only af11 testhi test use only m1 testlo test use only y4 testlo test use only af14 thermdn thermal diode cathode af13 thermdp thermal diode anode ae10 thermtrip# 1.5 v open drain output af7 tms jtag input w1 trdy# agtl i/o af15 trst# jtag input ad5 vcmos_ref cmos reference voltage af12 vcmos_ref cmos reference voltage ab1 vid0 voltage identification ac2 vid1 voltage identification ae2 vid2 voltage identification r3 vid25mv voltage identification af3 vid3 voltage identification a4 vref agtl reference voltage a21 vref agtl reference voltage n1 vref agtl reference voltage af9 vref agtl reference voltage af21 vref agtl reference voltage aa1 vref agtl reference voltage ab26 vref agtl reference voltage h26 vref agtl reference voltage e3 vtt_pwrgd vtt power good signal table 27. signal listing by signal name no. signal name signal buffer type
lv intel ? pentium ? iii processor 512k 56 datasheet table 28. voltage and no-connect ball locations signal name ball numbers nc a2, a5, a11, b1, c1, c22, d1, d26, e1, f1, l5, n4, n24, p1, p4, p5, p26, ad4, ad13, ad23, ae8, af17, af18 vcccore d6, d8, d10, d12, d14, d16, d18, d20, d22, e5, e7, e9, e11, e13, e15, e17, e19, e21, f6, f8, f10, f12, f14, f16, f18, f20, f22, g5, g21, h6, h22, j5, j21, k6, k22, l21, m6, m22, n5, n21, p6, p22, r5, r21, t6, t22, u5, u21, v6, v22, w5, w21, y6, y22, aa5, aa7, aa9, aa11, aa13, aa15, aa17, aa19, aa21, ab6, ab8, ab10, ab12, ab14, ab16, ab18, ab20, ab22, ac5, ac7, ac9, ac11, ac13, ac15, ac17, ac19, ac21 vtt a26, c5, c7, c9, c11, c13, c15, c17, c19, c21, d5, e4, e6, g4, g23, j4, j23, l4, l23, n23, r23, u23, v4, w23, aa4, aa23, ac4, ac23, ad6, ad8, ad12, ad14, ad18, ad20, ae3, ae18, af1, af2 vss a25, b2, b4, b6, b8, b10, b12, b14, b16, b18, b20, b22, b26, c23, c25, d2, d4, d7, d9, d11, d13, d15, d17, d19, d21, e8, e10, e12, e14, e16, e18, e20, e22, e25, f2, f4, f5, f7, f9, f11, f13, f15, f17, f19, f21, f23, g6, g22, g25, h2, h4, h5, h21, h23, j6, j22, j25, k2, k4, k5, k21, k23, l6, l22, l25, m2, m3, m4, m21, m23, n6, n22, n25, p2, p21, p23, r4, r6, r22, r25, t2, t5, t21, t23, u4, u6, u22, u25, v2, v5, v21, v23, w4, w6, w22, w25, y2, y5, y21, y23, aa6, aa8, aa10, aa12, aa14, aa16, aa18, aa20, aa22, aa25, ab2, ab5, ab7, ab9, ab11, ab13, ab15, ab17, ab19, ab21, ab23, ac6, ac8, ac10, ac12, ac14, ac16, ac18, ac20, ac22, ac25, ad2, ae1, ae5, ae7, ae9, ae11, ae13, ae15, ae17, ae19, ae21, ae23, ae26, af25, af26
lv intel ? pentium ? iii processor 512k datasheet 57 6.0 thermal specifications and design considerations this section provides needed data for designing a thermal solution. the lv intel pentium iii processor 512k uses micro flip-chip ball-grid-array packaging technology and has a junction temperature (t j ) specified at 100o c. 6.1 thermal specifications table 29 provides the thermal design power dissipation and maximum temperatures for the lv intel pentium iii processor 512k. systems should design for the highest possible processor power, even if a processor with a lower thermal dissipation is planned. a thermal solution should be designed to ensure the junction temperature never exceeds these specifications. 6.1.1 thermtrip# requirement in the event the processor drives the thermtrip# signal active during valid operation, both the v cc core and v tt supplies to the processor must be turned off to prevent thermal runaway of the processor. valid operation refers to the operating conditions where the thermtrip# signal is guaranteed valid. the time required from thermtrip# asserted to v cc core rail at 1/2 nominal is 5 seconds and thermtrip# asserted to v tt rail at 1/2 nominal is 5 seconds. table 29. lv intel pentium iii processor 512k thermal design power processor core frequency (mhz) processor core voltage (v) processor signature l2 cache size (kbytes) thermal design power 1, 2 (max, in w) maximum t j (c) 800 1.15 06b2 06b4 512 10.63 100 933 1.15 06b4 512 11.61 100 1000 1.15 06b4 512 12.1 100 notes: 1. these values are specified at nominal vcc core for the processor balls. 2. processor power includes the power dissipated by the processor core, the l2 cache, and the agtl bus termination. the maximum power for each of these components does not occur simultaneously. table 30. thermtrip# time requirement power rail power target time required for power drop v cc core 1/2 nominal v cc core 5 seconds v tt 1/2 nominal v tt 5 seconds note: once v cc core and v tt supplies are turned off the thermtrip# signal will be deactivated. system logic should ensure no ?unsafe? power cycling occurs due to this deassertion.
lv intel ? pentium ? iii processor 512k 58 datasheet 6.1.2 thermal diode the lv intel pentium iii processor 512k has an on-die thermal diode that can be used to monitor the die temperature (t j ). a thermal sensor located on the motherboard, or a stand-alone measurement kit, may monitor the die temperature of the processor for thermal management or instrumentation purposes. table 31 and table 32 provide the diode interface and specifications. note: the reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die. this is due to inaccuracies in the thermal sensor, on- die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the t j temperature can change. table 31. thermal diode interface ball name ball number description thermdp af13 thermal diode anode thermdn af14 thermal diode cathode table 32. thermal diode parameters symbol parameter 1 min typ max unit notes n diode ideality factor (5-150 a) 1.0011 1.0067 1.0122 1, 2, 3, 4, 6 n diode ideality factor (5-300 a) 1.0003 1.0091 1.0178 1, 2, 3, 5, 6 notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. characterized at 100 c 3. not 100% tested. specified by design/characterization. 4. specified for forward bias current = 5 a (min) and 150 a (max) 5. specified for forward bias current = 5 a (min) and 300 a (max) 6. the ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). i fw = i s e qv d nkt ? 1
lv intel ? pentium ? iii processor 512k datasheet 59 7.0 processor interface 7.1 alphabetical signals reference table 33. signal description (sheet 1 of 8) name type description a20m# i if the a20m# (address-20 mask) input signal is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1 mb boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. a[35:3]# i/o the a[35:3]# (address) signals define a 2 36 -byte physical memory address space. when ads# is active, these balls transmit the address of a transaction; when ads# is inactive, these balls transmit transaction type information. these signals must connect the appropriate balls of all agents on the processor system bus. the a[35:24]# signals are parity-protected by the ap1# parity signal, and the a[23:3]# signals are parity-protected by the ap0# parity signal. on the active-to-inactive transition of reset#, the processors sample the a[35:3]# balls to determine their power-on configuration. see the p6 family of processors hardware developer?s manual for details. ads# i/o the ads# (address strobe) signal is asserted to indicate the validity of the transaction address on the a[35:3]# balls. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. this signal must connect the appropriate balls on all processor system bus agents. aerr# i/o the aerr# (address parity error) signal is observed and driven by all processor system bus agents, and if used, must connect the appropriate balls on all processor system bus agents. aerr# observation is optionally enabled during power-on configuration; if enabled, a valid assertion of aerr# aborts the current transaction. if aerr# observation is disabled during power-on configuration, a central agent may handle an assertion of aerr# as appropriate to the error handling architecture of the system. ap[1:0]# i/o the ap[1:0]# (address parity) signals are driven by the request initiator along with ads#, a[35:3]#, req[4:0]#, and rp#. ap1# covers a[35:24]#, and ap0# covers a[23:3]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate balls of all processor system bus agents. bclk/bclk# i the bclk (bus clock) and bclk# (for differential clock) signals determines the bus frequency. all processor system bus agents must receive this signal to drive their outputs and latch their inputs on the rising edge of bclk. for differential clocking, all processor system bus agents must receive this signal to drive their outputs and latch their inputs on the bclk and bclk# crossing point. all external timing parameters are specified with respect to the bclk signal.
lv intel ? pentium ? iii processor 512k 60 datasheet berr# i/o the berr# (bus error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor system bus agents, and must connect the appropriate balls of all such agents, if used. however, the lv intel pentium iii processor 512k does not observe assertions of the berr# signal. berr# assertion conditions are configurable at a system level. assertion options are defined by the following options: ? enabled or disabled. ? asserted optionally for internal errors along with ierr#. ? asserted optionally by the request initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. binit# i/o the binit# (bus initialization) signal may be observed and driven by all processor system bus agents. when used, it must connect the appropriate balls of all such agents. if the binit# driver is enabled during power on configuration, binit# is asserted to signal any bus condition that prevents reliable future information. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, all bus state machines are reset and any data that is in transit is lost. all agents reset their rotating id for bus arbitration to the state after reset, and internal count information is lost. the l1 and l2 caches are not affected. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. bnr# i/o the bnr# (block next request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wire-or signal that must connect the appropriate balls of all processor system bus agents. in order to avoid wire-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. bp[3:2]# i/o the bp[3:2]# (breakpoint) signals are outputs from the processor that indicate the status of breakpoints. bpm[1:0]# i/o the bpm[1:0]# (breakpoint monitor) signals are breakpoint and performance monitor signals. they are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpri# i the bpri# (bus priority request) signal is used to arbitrate for ownership of the processor system bus. it must connect the appropriate balls of all processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed. it then releases the bus by deasserting bpri#. table 33. signal description (sheet 2 of 8) name type description
lv intel ? pentium ? iii processor 512k datasheet 61 br0# br1# i/o i the br0# and br1#(bus request) balls drive the breq[1:0]# signals in the system. the breq[1:0]# signals are interconnected in a rotating manner to individual processor balls. the following table gives the rotating interconnect between the processor and bus signals. during power-up configuration, the central agent asserts the br0# bus signal in the system to assign the symmetric agent id to the processor. the processor samples its br0# ball on the active-to-inactive transition of the reset# to obtain its symmetric agent id. the processor asserts the br0# ball to request the system bus. all agents then configure their balls to match the appropriate bus signal protocol, as shown in the following table. for uniprocessor designs, br0# must be connected to a 10-56 ? resistor to v ss . bsel[1:0] o the bsel[1:0] (select processor system bus speed) signals are used to configure the processor for the system bus frequency. the chipset and system clock generator also uses the bsel signals. the vtt_pwrgd signal informs the processor to output the bsel signals. during power up the bsel signals are indeterminate for a small period of time. the chipset and clock generator should not sample the bsel signals until the vtt_pwrgd signal is asserted. the assertion of the vtt_pwrgd signal indicates that the bsel signals are stable and driven to a final state by the processor. please refer to figure 16 for the timing relationship between the bsel and vtt_pwrgd signals. the following table shows the encoding scheme for bsel[1:0]. the lv pentium iii processor 512k supports only a 133 mhz system bus frequency. if another frequency is used, the processor is not guaranteed to function properly. clkref i in single-ended clock mode the clkref input is a filtered 1.25v supply voltage for the processor pll. a voltage divider and decoupling solution is provided by the motherboard. refer to th e lv intel ? pentium ? iii processor 512k dual processor platform design guide for i mplementation details. when the processor operates in differential clock mode, this signal becomes bclk#. d[63:0]# i/o the d[63:0]# (data) signals are the data signals. these signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate balls on all such agents. the data driver asserts drdy# to indicate a valid data transfer. table 33. signal description (sheet 3 of 8) name type description br0# (i/o) and br1# signals rotating interconnect bus signal agent 0 ball agent 1 ball breq0# br0# br1# breq1# br1# br0# br0# (i/o) and br1# signals rotating interconnect ball sampled active in reset# agent id br0# 0 br1# 3 bsel[1:0] system bus frequency 11 133 mhz
lv intel ? pentium ? iii processor 512k 62 datasheet dbsy# i/o the dbsy# (data bus busy) signal is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate balls on all processor system bus agents. defer# i the defer# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or i/o agent. this signal must connect the appropriate balls of all processor system bus agents. dep[7:0]# i/o the dep[7:0]# (data bus ecc protection) signals provide optional ecc protection for the data bus. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate balls of all processor system bus agents that use them. the dep[7:0]# signals are enabled or disabled for ecc protection during power on configuration. drdy# i/o the drdy# (data ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-cycle data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate balls of all processor system bus agents. ferr# o the ferr# (floating-point error) signal is asserted when the processor detects an unmasked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems that use ms-dos*-type floating-point error reporting. flush# i when the flush# input signal is asserted, processors write back all data in the modified state from their internal caches and invalidate all internal cache lines. at the completion of this operation, the processor issues a flush acknowledge transaction. the processor does not cache any new data while the flush# signal remains asserted. flush# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. on the active-to-inactive transition of reset#, each processor samples flush# to determine its power-on configuration. see the p6 family of processors hardware developer?s manual for details. this signal must be connected to a 150 ? resistor to v cc cmos1.5 . refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details and resistor tolerance. hit# hitm# i/o i/o the hit# (snoop hit) and hitm# (hit modified) signals convey transaction snoop operation results, and must connect the appropriate balls of all processor system bus agents. any such agent may assert both hit# and hitm# together to indicate that it requires a snoop stall; it can be continued by reasserting hit# and hitm# together. ierr# o the ierr# (internal error) signal is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the processor system bus. this transaction may be converted to an external error signal (e.g., nmi) by system core logic. the processor keeps ierr# asserted until the assertion of reset#, binit#, or init#. ignne# i the ignne# (ignore numeric error) signal is asserted to force the processor to ignore a numeric error and to continue to execute non-control floating-point instructions. if ignne# is deasserted, the processor generates an exception on a non-control floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. table 33. signal description (sheet 4 of 8) name type description
lv intel ? pentium ? iii processor 512k datasheet 63 init# i the init# (initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (l1 or l2) caches or floating-point registers. each processor then begins execution at the power-on reset vector that is configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate balls of all processor system bus agents. when init# is sampled active on the active to inactive transition of reset#, the processor executes its built-in self-test (bist). lint0/intr lint1/nmi i the lint[1:0] (local apic interrupt) signals must connect the appropriate balls of all apic bus agents, including all processors and the core logic or i/o apic component. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a non-maskable interrupt. intr and nmi are backward compatible with the signals of those names on the intel ? pentium ? processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space that is to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these balls as lint[1:0] is the default configuration. lock# i/o the lock# signal indicates to the system that a transaction must occur atomically. this signal must connect the appropriate balls of all processor system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor system bus throughout the bus-locked operation and ensure the atomicity of lock. nchctrl i the nchctrl input signal provides agtl pull-down strength control. the lv intel pentium iii processor 512k samples this input to determine the n-channel device strength for pull-down when it is the driving agent. this signal must be connected to a 14 ? resistor to v tt . refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. picclk i the picclk (apic clock) signal is an input clock to the processor and core logic or i/o apic that is required for operation of all processors, core logic, and i/o apic components on the apic bus. picd[1:0] i/o the picd[1:0] (apic data) signals are used for bidirectional serial message passing on the apic bus. picd[1:0] must connect the appropriate balls of all processors and core logic or i/o apic components on the apic bus. pll1, pll2 i the lv intel pentium iii processor 512k has an internal analog pll clock generator that requires a quiet power supply. pll1 and pll2 are inputs to this pll and must be connected to v tt through a low pass filter that minimizes jitter. refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. prdy# o the prdy (probe ready) signal is a processor output used by debug tools to determine processor debug readiness. preq# i the preq# (probe request) signal is used by debug tools to request debug operation of the processors. table 33. signal description (sheet 5 of 8) name type description
lv intel ? pentium ? iii processor 512k 64 datasheet pwrgood i the pwrgood (power good) signal is processor input. the processor requires this signal to be a clean indication that the clocks and power supplies (v cc core , etc.) are stable and within their specifications. clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in table 16 , and be followed by a 1 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# i/o the req[4:0]# (request command) signals must connect the appropriate balls of all processor system bus agents. they are asserted by the current bus owner over two clock cycles to define the currently active transaction type. reset# i asserting the reset# signal resets all processors to known states and invalidates their l1 and l2 caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least one millisecond after v cc core and clk have reached their proper specifications. upon observing active reset#, all processor system bus agents will deassert their outputs within two clocks. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the p6 family of processors hardware developer?s manual for details. the processor may have its outputs tri-stated via power-on configuration. otherwise, if init# is sampled active during the active-to-inactive transition of reset#, the processor will execute its built-in self-test (bist). whether or not bist is executed, the processor will begin program execution at the power on reset vector (default 0_ffff_fff0h). reset# must connect the appropriate balls of all processor system bus agents. reset# is the only agtl signal that does not have on-die termination. therefore, it is necessary to place a discrete 56 ? resistor to v tt . refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. rp# i/o the rp# (request parity) signal is driven by the request initiator, and provides parity protection on ads# and req[4:0]#. it must connect the appropriate balls of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this definition allows parity to be high when all covered signals are high. rs[2:0]# i/o the rs[2:0]# (response status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate balls of all processor system bus agents. rsp# i the rsp# (response parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect the appropriate balls of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. when rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by an agent that can guarantee correct parity. rttctrl i the rttctrl input signal provides agtl termination control. the lv intel pentium iii processor 512k samples this input to set the termination resistance value for the on-die agtl termination. this signal must be connected to a 56 ? resistor to v ss on a uniprocessor platform or a 68 ? resistor to v ss on a dual- processor platform. refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. table 33. signal description (sheet 6 of 8) name type description
lv intel ? pentium ? iii processor 512k datasheet 65 slewctrl i the slewctrl input signal provides agtl slew rate control. the lv intel pentium iii processor 512k samples this input to determine the slew rate for agtl signals when it is the driving agent. this signal must be connected to a 110 ? resistor to v ss . refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. slp# i the slp# (sleep) signal, when asserted in stop-grant state, causes processors to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will only recognize assertions of the slp#, stpclk#, and reset# signals while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and apic processor core units. smi# i the smi# (system management interrupt) signal is asserted asynchronously by system logic. upon accepting a system management interrupt, processors save the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. stpclk# i the stpclk# (stop clock) signal, when asserted, causes processors to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and apic units. the processor continues to snoop bus transactions and latch interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units, services pending interrupts while in the stop-grant state, and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck i the tck (test clock) signal provides the clock input for the processor test bus (also known as the test access port). tdi i the tdi (test data in) signal transfers serial test data into the processor. tdi provides the serial input that is needed for jtag specification support. tdo o the tdo (test data out) signal transfers serial test data out of the processor. tdo provides the serial output that is needed for jtag specification support. testhi[2:1] i the testhi[2:1] (test input high) signals are used during processor test and need to be individually pulled up to v tt during normal operation. refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. testlo[2:1] i the testlo[2:1] (test input low) signals are used during processor test and need to be pulled to ground during normal operation. refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. thermdn o thermal diode cathode. used to calculate core (junction) temperature. see section 6.0 . thermdp i thermal diode anode. used to calculate core (junction) temperature. see section 6.0 . table 33. signal description (sheet 7 of 8) name type description
lv intel ? pentium ? iii processor 512k 66 datasheet thermtrip# o the processor protects itself from catastrophic overheating through the use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. the processor stops all execution when the junction temperature exceeds approximately 135 c. this is signaled to the system by the thermtrip# (thermal trip) ball. once activated, the signal remains latched, and the processor remains stopped, until reset# goes active or core power is removed. there is no hysteresis built into the thermal sensor itself; when the die temperature drops below the trip level, a reset# pulse will reset the processor and execution continues. if the temperature does not drop below the trip level, the processor drives thermtrip# and remains stopped. in the event the processor drives the thermtrip# signal active during valid operation, both the v cc core and v tt supplies to the processor must be turned off to prevent thermal runaway of the processor. valid operation refers to the operating conditions where the thermtrip# signal is guaranteed valid. the time required from thermtrip# asserted to v cc core rail at 1/2 nominal is 5 seconds and thermtrip# asserted to v tt rail at 1/2 nominal is 5 seconds. once v cc core and v tt supplies are turned off the thermtrip# signal is deactivated. system logic should ensure that no ?unsafe? power cycling occurs due to this deassertion. tms i the tms (test mode select) signal is a jtag specification support signal used by debug tools. trdy# i/o the trdy# (target ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate balls of all processor system bus agents. trst# i the trst# (test reset) signal resets the test access port (tap) logic. trst# must be driven low during power on reset. v cmos_ref i the v cmos_ref input ball supplies non-agtl reference voltage; the voltage level should be nominally 2/3 of v cmos . v cmos_ref is used by the non-agtl receivers to determine if a signal is a logical 0 or a logical 1. the thevenin equivalent impedance of the vcmos_ref generation circuits must be less than 0.5 k ? /1 k ? (i.e., top resistor 500 ? , bottom resistor 1 k ? ). refer to the lv intel ? pentium ? iii processor 512k dual processor platform design guide for implementation details. vid [3:0,25mv] o the vid[3:0, 25 mv] (voltage id) balls can be used to support automatic selection of power supply voltages. these balls are cmos signals that must be pulled up to 3.3 v power rail with 1 k ? resistors. the vid balls are needed to cleanly support voltage specification variations on processors. see table 5 for definitions of these balls. the power supply must supply the voltage that is requested by these balls, or disable itself. v ref i the v ref input balls supply the agtl reference voltage; the voltage level is typically 2/3 of v tt . v ref is used by the agtl receivers to determine if a signal is a logical 0 or a logical 1. v tt_pwrgd i the vtt_pwrgd signal informs the system that the vid/bsel signals are in their correct logic state. during power-up, the vid signals will be in a indeterminate state for a small period of time. the voltage regulator or the vrm should not sample and/ or latch the vid signals until the vtt_pwrgd signal is asserted. the assertion of the vtt_pwrgd signal indicates that the vid signals are stable and are driven to the final state by the processor. refer to figure 16 for the power-up timing sequence for the vtt_pwrgd and the vid signals. table 33. signal description (sheet 8 of 8) name type description
lv intel ? pentium ? iii processor 512k datasheet 67 7.2 signal summaries table 34. input signals name active level clock signal group qualified a20m# low asynch cmos always bclk high ? system bus always bclk# low ? system bus always bpri# low bclk system bus always defer# low bclk system bus always flush# low asynch cmos always ignne# low asynch cmos always init# low asynch cmos always intr high asynch cmos apic disabled mode lint[1:0] high asynch cmos apic enabled mode nchctrl n/a asynch power/other nmi high asynch cmos apic disabled mode picclk high ? apic always preq# low asynch cmos always pwrgood high asynch cmos always reset# low bclk system bus always rsp# low bclk system bus always rttctrl n/a asynch power/other slewctrl n/a asynch power/other slp# low asynch implementation smi# low asynch cmos always stpclk# low asynch cmos always tck high ? jtag tdi high tck jtag tms high tck jtag trst# low asynch jtag vri# low bclk system bus always vtt_pwrgd high asynch power/other
lv intel ? pentium ? iii processor 512k 68 datasheet table 35. output signals name active level clock signal group bsel[1:0] high asynch open-drain ferr# low asynch open-drain ierr# low asynch open-drain prdy# low bclk system bus tdo high tck jtag thermtrip# low asynch open-drain vid[3:0, 25mv] asynch power/other table 36. input/output signals (single driver) name active level clock signal group qualified a[35:3]# low bclk system bus ads#, ads#+1 ads# low bclk system bus always ap[1:0]# low bclk system bus ads#, ads#+1 bp[3:2]# low bclk system bus always bpm[1:0]# low bclk system bus always br0# low bclk system bus always d[63:0]# low bclk system bus drdy# dbsy# low bclk system bus always dep[7:0]# low bclk system bus drdy# drdy# low bclk system bus always lock# low bclk system bus always req[4:0]# low bclk system bus ads#, ads#+1 rp# low bclk system bus ads#, ads#+1 rs[2:0]# low bclk system bus always trdy# low bclk system bus response phase table 37. input/output signals (multiple driver) name active level clock signal group qualified aerr# low bclk system bus ads#+3 berr# low bclk system bus always binit# low bclk system bus always bnr# low bclk system bus always hit# low bclk system bus always hitm# low bclk system bus always picd[1:0] high picclk apic always
datasheet 1 contents 1 related documents ............................................................................................................. ......... 9 2 lv/ulv intel? pentium? iii processor 512k cpuid .................................................................15 3 system bus signal groups...................................................................................................... ...16 4 bsel[1:0] encoding............................................................................................................ ........17 5 lv intel pentium iii processor 512k vid values ........................................................................22 6 lv intel pentium iii processor 512k absolute maximum ratings ..............................................24 7 power specifications for lv intel pentium iii processor 512k ...................................................25 8vcc core static and transient tolerance ...................................................................................27 9 agtl signal group levels specifications..................................................................................28 10 processor agtl bus specifications...........................................................................................2 8 11 clkref, apic, tap, cmos, and open-drain signal group dc specifications ......................29 12 system bus clock ac specifications (differential).....................................................................30 13 system bus clock ac specifications (133 mhz, single-ended) ................................................31 14 valid lv intel pentium iii processor 512k frequencies .............................................................32 15 agtl signal groups ac specifications .....................................................................................32 16 cmos and open-drain signal groups ac specifications .........................................................32 17 reset configuration ac specifications and power on timings .................................................33 18 apic bus signal ac specifications ............................................................................................ 33 19 tap signal ac specifications................................................................................................. ....34 20 bclk (differential) dc specifications and ac signal quality specifications .............................40 21 bclk (single-ended) dc specifications and ac signal quality specifications.........................40 22 picclk dc specifications and ac signal quality specifications ..............................................41 23 133 mhz agtl signal group overshoot/undershoot tolerance at the processor core.......................................................................................................... .......43 24 non-agtl signal group overshoot/undershoot tolerance at the processor core ..................43 25 micro-fcbga package mechanical specifications ....................................................................46 26 signal list by ball number................................................................................................... .......51 27 signal listing by signal name ................................................................................................ ....54 28 voltage and no-connect ball locations .....................................................................................56 29 lv intel pentium iii processor 512k thermal design power .....................................................57 30 thermtrip# time requirement ..............................................................................................57 31 thermal diode interface ...................................................................................................... .......58 32 thermal diode parameters..................................................................................................... ....58 33 signal description........................................................................................................... ............59 34 input signals ................................................................................................................ ...............67 35 output signals ............................................................................................................... .............68 36 input/output signals (single driver) ......................................................................................... ..68 37 input/output signals (multiple driver)....................................................................................... ..68
contents 2 datasheet
datasheet 1 contents 1 agtl bus topology ............................................................................................................. ......11 2 stop clock state machine ...................................................................................................... ....12 3 differential/single-ended clocking example ..............................................................................15 4 single ended clock bsel circuit (133 mhz) .............................................................................18 5 differential clock bsel circuit ............................................................................................... ....19 6 pll filter .................................................................................................................... ................21 7v tt power good and bus select interconnect diagram ............................................................23 8 power supply current slew rate (dicc core /dt) .........................................................................26 9vcc core static and transient tolerance ...................................................................................27 10 bclk (single ended)/picclk/tck generic clock timing waveform.......................................35 11 differential bclk/bclk# waveform (common mode) ..............................................................35 12 bclk/bclk# waveform (differential mode) ..............................................................................36 13 valid delay timings .......................................................................................................... ..........36 14 setup and hold timings ....................................................................................................... ......37 15 cold/warm reset and configuration timings ............................................................................37 16 power-on sequence and reset timings ...................................................................................38 17 test timings (boundary scan) ................................................................................................. ..39 18 test reset timings........................................................................................................... ..........39 19 bclk (single-ended)/picclk generic clock waveform ..........................................................41 20 maximum acceptable overshoot/undershoot waveform...........................................................42 21 noise estimation............................................................................................................. ............45 22 micro-fcbga package ? top and bottom isometric views.......................................................47 23 micro-fcbga package ? top and side views ..........................................................................48 24 micro-fcbga package - bottom view .......................................................................................49 25 ball map - top view.......................................................................................................... ..........50
contents 2 datasheet
datasheet 1 contents 1.0 introduction ............................................................................................................................... ..... 7 1.1 overview.................................................................................................................... ........... 7 1.2 terminology ................................................................................................................. ......... 8 1.3 related documents ........................................................................................................... ...9 2.0 processor features .....................................................................................................................10 2.1 512-kbyte on-die integrated l2 cache .............................................................................10 2.2 data prefetch logic ......................................................................................................... ...10 2.3 processor system bus and v ref.............................................................................................................. 10 2.4 differential clocking ....................................................................................................... .....11 2.5 clock control and low power states .................................................................................11 2.5.1 normal state?state 1 ...........................................................................................12 2.5.2 autohalt power down state?state 2 ................................................................12 2.5.3 stop-grant state?state 3 .....................................................................................13 2.5.4 halt/grant snoop state?state 4 ........................................................................13 2.5.5 sleep state?state 5 .............................................................................................13 2.5.6 clock control .........................................................................................................14 2.6 power and ground balls .....................................................................................................1 4 2.7 processor system bus clock and processor clocking ......................................................14 2.8 processor system bus unused balls .................................................................................15 2.9 lv intel pentium iii processor 512k cpuid.......................................................................15 3.0 electrical specifications .............................................................................................................16 3.1 processor system bus signal groups................................................................................16 3.1.1 asynchronous vs. synchronous for system bus signals ......................................17 3.1.2 system bus frequency select signals ..................................................................17 3.2 single-ended clocking bsel[1:0] implementation.............................................................17 3.3 differential host bus clocking routing ...............................................................................18 3.3.1 differential clocking bsel[1:0] implementation ....................................................18 3.4 signal state in low-power states ......................................................................................19 3.4.1 system bus signals ...............................................................................................19 3.4.2 cmos and open-drain signals.............................................................................19 3.4.3 other signals .........................................................................................................19 3.5 test access port (tap) connection ...................................................................................20 3.6 power supply requirements ..............................................................................................20 3.6.1 decoupling guidelines ...........................................................................................20 3.6.2 processor vcc core decoupling ...........................................................................20 3.6.3 voltage planes.......................................................................................................21 3.7 voltage identification ...................................................................................................... ....21 3.8 system bus clock and processor clocking........................................................................24 3.9 maximum ratings ............................................................................................................. ..24 3.10 dc specifications .......................................................................................................... .....25 3.11 ac specifications.......................................................................................................... ......30 3.11.1 system bus, clock, apic, tap, cmos, and open-drain ac specifications........30 4.0 system signal simulations .........................................................................................................40 4.1 system bus clock (bclk) and picclk dc specifications and ac signal quality specifications ..........................................................40 4.2 agtl ac signal quality specifications ..............................................................................42 4.3 non-agtl signal quality specifications ............................................................................43
contents 2 datasheet 4.3.1 pwrgood signal quality specification............................................................... 44 4.3.2 vtt_pwrgd signal quality specification............................................................ 44 5.0 mechanical specifications .......................................................................................................... 46 5.1 surface mount micro-fcbga package .............................................................................. 46 5.2 signal listings............................................................................................................. ........ 50 6.0 thermal specifications and design considerations ................................................................ 57 6.1 thermal specifications ...................................................................................................... .57 6.1.1 thermtrip# requirement .................................................................................. 57 6.1.2 thermal diode ....................................................................................................... 58 7.0 processor interface ..................................................................................................................... 59 7.1 alphabetical signals reference.......................................................................................... 59 7.2 signal summaries............................................................................................................ ... 67
intel? pentium? iii processors for embedded computing us home | intel worldwide where to buy | training & events | contact us | about intel advanced embedded intel? architecture print this page embedded & flash memory embedded intel? architecture processors intel? pentium? iii processors pentium? iii processors where to buy product highlights 1.26 ghz 370-pin fc-pga2 package with 512 kb advanced transfer cache (on-die, full-speed l2 cache) 1 ghz, 866, 850, 733, 700 and 600 mhz, 370-pin fc-pga package 700, 500 and 400 mhz bga2 package 1 ghz, 866 and 733 mhz processor supports 133 mhz processor side bus 256 kbytes advanced transfer cache (on-die, full-speed l2 cache) compatible with intel? 840, 815, 815e, 810e2, 810 chipsets; intel? 82801e c-ich; intel? 440bx agpset and 440mx chipset communications industrial pc student computing station interactive clients pentium? iii processors documentation product number core speed (mhz) l2 cache external bus speed (mhz) thermal design power (max) voltage t junction package rk80530kz012512 1.26 ghz 512k 133 29.5w 1.45v 69c* 370 fc-pga2 rb80526pz001256 1 ghz 256k 133 29.0w 1.75v 75c 370 fc-pga rb80526py001256 + 1 ghz 256k 100 29.0w 1.75v 75c 370 fc-pga rb80526pz866256 866 256k 133 26.1w 1.75v 80c 370 fc-pga rb80526py850256 850 256k 100 25.7w 1.75v 80c 370 fc-pga rb80526pz733256 733 256k 133 22.8w 1.75v 80c 370 fc-pga rb80526py700256 700 256k 100 21.9w 1.75v 80c 370 fc-pga rb80526py600256 600 256k 100 19.6w 1.75v 82c 370 fc-pga * t case, not t junction + for existing embedded applications using the intel? 440bx chipset only. drop ship only. low voltage pentium? iii processors documentation product number core speed (mhz) l2 cache external bus speed (mhz) thermal design power (max) voltage t junction package RJ80530KZ933512** 933** 512k 133 12.2w 1.15v 0-100c 479 fcbga rj80530kz800512** 800** 512k 133 11.2w 1.15v 0-100c 479 fcbga ** supports dual processing when paired with third party chipsets. pentium? iii processors - low power documentation product number core speed (mhz) l2 cache external bus speed (mhz) thermal design power (max) voltage t junction package file:///c|/documents%20and%20settings/lakshmi...20processors%20for%20embedded%20computing.htm (1 of 3) [1/25/2005 4:02:57 pm]
intel? pentium? iii processors for embedded computing kc80526gy850256*** 700*** 256k 100 16.12w 1.35v 0-100c 495 bga kc80526ly500256 500 256k 100 12.2w 1.35v 0-100c 495 bga kc80526ly400256 400 256k 100 10.1w 1.35v 0-100c 495 bga *** intel pentium iii processor at 850/700 mhz featuring intel? speedstep? technology (1.6v/1.35v respectively). pentium? iii processors intel? pentium? iii processor for embedded computing the pentium? iii processor is ideal for high-performance, connected applications designed for dedicated use ? such as high-end communication appliances and infrastructure, interactive clients and industrial automation. the pentium iii processor-based hardware and software building blocks, plus design support, help speed the design process and lower total development costs. the intel pentium iii processor at 1.26 ghz, 1 ghz, 866, 850, 733, 700 and 600 mhz offers high performance for the most demanding applications. it comes in flip-chip pin grid array (fc-pga) and flip-chip pin grid array 2 (fc-pga2) packages that allow for small form factor, low profile designs. this is especially important in rack mounted environments, such as compactpci* (cpci), where board height is critical. performance and low power the pentium iii processor - low power at 400, 500, 700**, 800 and 933 mhz combines performance with small form factor and low power, making it ideal for the most power sensitive, space-constrained environments. it comes in a bga2 or fcbga package which is the smallest pentium iii processor package available. intel chipsets the intel pentium iii and celeron? processors, both in the fc-pga package, are validated with multiple chipsets for maximum flexibility. the pentium iii processor, combined with the intel? 840 chipset in dual- processor and uni-processor configurations deliver a high-performance, high-bandwidth platform for computer-intensive applications. with the intel? 815, 815e, 810 or 440bx chipsets, you can design a scalable board supporting both the pentium iii and celeron processors. the intel 840 chipset features include support for 100 or 133 mhz system bus, single or dual processor configuration, ecc on memory, high memory bandwidth, large memory capacity, agp 4x, and a second pci bus (64bit / 66 mhz) for high performance i/o. the intel 815 and 815e chipsets provide the highest degree of processor scalability supporting the intel celeron processor at 566 mhz and celeron processor - ultra low power at 300 mhz to the pentium iii processor at 1 ghz to the pentium iii processor with 512k cache at 1.26 ghz. the chipsets support processor side bus speeds of 66, 100 and 133 mhz. the intel 815 and 815e chipsets also provide graphics scalability through the use of intel graphics, an add-in graphics performance accelerator (gpa) card, or an add-in agp 4x card. the intel 815/e gmch is validated for use with the intel? 82801e communications i/o controller hub (c-ich). the intel 810 and 810e2 chipsets support the celeron processors in fc-pga2, fc-pga and ppga packages and the pentium iii processor in fc-pga2, fc-pga. these chipsets reduce overall system cost by integrating graphics into the memory controller. the 810 chipset optimizes system memory arbitration, similar to agp technology, resulting in a more responsive and cost-effective system. the intel 810e2 chipset design is extended to support 133 mhz processor side bus speeds, feature internal lan capability as well as four usb ports, and support for ata/100. the intel 810 and 810e gmchs are also validated for use with the intel 82801e communications i/o controller hub c-ich. the intel? 440bx agpset includes support for ecc on memory, agp 2x and up to 1 gigabyte memory. the intel 440bx agpset also supports the pentium iii processor - low power in a bga2 and module package. the intel? 440mx chipset supports intel celeron processors - low power and the pentium iii processor - low power. it provides support for usb, acpi power management and ac-97 link. a single component, it integrates the north bridge and south bridge into a single chip. the 440mx chipset features low power dissipation that makes it ideal for fanless applications. design support for fast time-to-market with the scalable performance board design program, developers can design a single board that can file:///c|/documents%20and%20settings/lakshmi...20processors%20for%20embedded%20computing.htm (2 of 3) [1/25/2005 4:02:57 pm]
intel? pentium? iii processors for embedded computing accept intel pentium iii and celeron processors without modification. using the design guides for the 815, 815e, 810 or 440bx chipsets, developers can reduce the design and validation effort for multiple designs, lower their total cost of ownership, get to market faster and build applications with a wide range of price and performance options. intel development kits expedite development of high-performance applications that take advantage of pentium iii processors supported for extended life cycles. development kits that feature the pentium iii processor are: l pentium iii processor/840 development kit l intel 815e scalable performance board development kit l intel 440bx scalable performance board development kit l intel 440mx scalable low power board development kit design solutions l firewall/vpn appliance l network attached storage back to top copyright 2005 intel corporation ?2005 intel corporation file:///c|/documents%20and%20settings/lakshmi...20processors%20for%20embedded%20computing.htm (3 of 3) [1/25/2005 4:02:57 pm]

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